SU949789A1

SU949789A1 - Pulse repetition frequency multiplier

Info

Publication number: SU949789A1
Application number: SU803226830A
Authority: SU
Inventors: Владимир Иванович Микулович; Николай Николаевич Скриган
Original assignee: Белорусский Ордена Трудового Красного Знамени Государственный Университет Им.В.И.Ленина
Priority date: 1980-12-29
Filing date: 1980-12-29
Publication date: 1982-08-07

Description

Изобретение относитс к измерительной и импульсной технике и может найти применение в устройствах различного назначени , в частности в устройствах автоматизированного контроле: состо ни машин и механизмов с вращающимис част ми с помощью электронных методов анализа и измерени частотных составл ющих вибраций и акустических шумов.The invention relates to measuring and pulse technology and can be used in devices for various purposes, in particular in automated control devices: the state of machines and mechanisms with rotating parts using electronic methods for analyzing and measuring the frequency components of vibrations and acoustic noise.

Известен умножитель частоты следовани импульсов, содержащий делитель опорной частоты, входной и выходной формирователи импульсов, счетчик импульсов, блок управлени , запоминающий регистр и блок элементов И 1 .A pulse multiplying frequency multiplier is known, which contains a reference frequency divider, input and output pulse shapers, a pulse counter, a control unit, a memory register, and a block of And 1 elements.

Однако известное устройство обеспечивает недостаточно высокую точность умножени .However, the known device does not provide a high enough accuracy of multiplication.

Наиболее близкий по технической сущности к изобретению умножитель частоты следовани импульсов содержит генератор опорной.частоты, выход которого соединен со счетным входом первого делител частоты и первым входом блока управлени (входного формировател ), второй вход которого подключен к входной шине, а первый и второй выходы - соответственноThe pulse frequency multiplier closest to the invention to the invention comprises a reference frequency generator, the output of which is connected to the counting input of the first frequency divider and the first input of the control unit (input driver), the second input of which is connected to the input bus, and the first and second outputs respectively

к установочному входу счетчика импульсов и управл ющему входу первого запоминающего регистра, группа входов которого соединена с выходами счетчика импульсов, сумматор, элемент запрета, блок переноса и выходной формирователь 2.to the setup input of the pulse counter and the control input of the first memory register, the group of inputs of which is connected to the outputs of the pulse counter, the adder, the prohibition element, the transfer unit and the output driver 2.

Это устройство также обеспечивает недостаточно высокую точность умно10 жени .This device also provides an insufficiently high accuracy of smart 10.

Цель изобретени - повьлшение точностн умножени .The purpose of the invention is to increase the accuracy of multiplication.

Дл достижени указанной цели в умножитель частоты следовани импуль15 сов , содержсцций генератор опорной частоты, выход которого соединен со счетным входом делител частоты и пepвы л входом блока управлени , второй вход которого подключен к входной To achieve this goal, a pulse frequency multiplier in the frequency multiplier, a reference frequency generator, the output of which is connected to the counting input of the frequency divider and the first input of the control unit, the second input of which is connected to the input

20 шине, а первый и второй выходы - соответственно к установочному входу счетчика импульсов и управл ющему входу первого запоминающего регистра, группа входов которого соединена с 20, and the first and second outputs, respectively, to the setup input of the pulse counter and the control input of the first memory register, the group of inputs of which is connected to

Claims

25 outputs of the pulse counter, the second storage register and the division block are entered, the control inputs of which are connected respectively to the third and fourth outputs of the control unit, the first group of inputs of the division block is connected to the outputs of the first borrowing register, the second group of inputs is with the code input buses the multiplication factor, and the outputs - with the group of inputs of the second memory register, the outputs of which are connected to the group of inputs of the frequency divider, while the counting input of the pulse counter is connected to the output of the generator pn frequency. The drawing shows the structures on the scheme of the proposed device. The device contains a reference frequency generator 1, a counter 2 pulse memory registers 3 and 4, divide 5 frequencies with a fractional variable division factor, division unit 6, control unit 7, input bus 8, output bus 9 and bus 10 input the multiplication factor code. The frequency multiplier works as follows. Generator 1 pulses are received during the period of the multiplied frequency at the input of counter 2. By the time of arrival of the next input pulse, counter 2 records the number N, which is equal to N Te, -fo, De Tgx is the period of the input signal, and fo is the frequency of the pulse of the generator 1, L T is the measurement error of the Tech value / due to the quantization of numbers in the counter 2. Block 7 generates a rectangular pulse which, with gating signal 1 and with different delays, arrives at the outputs block 7.. The first pulse appears at the second output of block 7, and, arriving at the control input of register 3, the number N is recorded. Then, with a delay of the establishment of transients in register 3, pulses appear at the first and fourth outputs of block 7 The first of these sets up the initial state of counter 2, and in the second it issues a start command to the retention unit. The block 6 dividing the block command performs an arithmetic division of the number N stored in register 3 by the multiplication factor k, the value of which is fed to the bus 10. The pulse from the third output of the block arrives with the delay necessary to perform the division operation and writing the result to the register 4. The number P N / k determines the division factor of the divider 5. The frequency of the pulses at the output of the divider 5 is equal to -Г where lR is the error in performing the division operation. Substituting the value of P in the last expression, you can get .K., PK-f2 -% X-f (T-.4P). The second term determines the error l. If the accuracy of the division operation is such that kAP "lT, then the maximum error is equal. Thus, the frequency multiplication error in the proposed multiplier is less than that of the prototype, which allows frequency multiplication in a wider range. Claims An impulse frequency multiplier comprising a frequency generator, the output of which is connected to the counting input of the first frequency splitter and the first input of the control unit, the second input of which is connected to the input bus, and the first and second outputs respectively to the setting input of the pulse counter and the control the input of the first memory register, the group of inputs of which is connected to the outputs of the pulse counter, characterized in that, in order to increase the multiplication accuracy, a second memory is entered into it the register and division block, the control inputs of which are connected to the third and fourth outputs of the control unit, the first group of inputs of the division block is connected to the outputs of the first memory register, the second group of inputs to the input buses of the multiplication factor code, and the outputs to the group of inputs the second memory register, the outputs of which are connected to a group of inputs of the first frequency divider, while the counting input of the pulse counter is connected to the output of the reference frequency generator. Sources of information taken into account during the examination 1. USSR author's certificate No. 357668, cl. And 03 K 5/01, 1972.

2. USSR author's certificate No. 705657, cl. H 03 K 5/01, 1977.