SU849226A1 - Correlation device for determining delay - Google Patents

Description

(54) CORRELATION DEVICE FOR DETERMINATION

one

The invention relates to specialized digital computing equipment and can be used to determine the delay between the source and reference signals in correlation velocity meters and range finders.

A correlation meter is known that contains delay lines, integrators, multiplication units, switches, and decoders 1.,

However, the device does not provide high accuracy over a wide range of measurable delays and requires a lot of equipment.

Closest to the invention is a correlation device for determining the delay, containing a clock divider with a variable division factor and a multiplexer, which allows to provide a low-ranging bit 2 over a wide range of measured delays.

A disadvantage of the known device is the inconsistency of the analysis for different ordinates of the correlation function, determined by the discrete nature of the clock frequency. (a change in the division factor of the clock divider), which is defined by the delay

It does not have a high accuracy of determining the delay time with a relatively high device speed, or a low device speed with a relatively high accuracy with a large amount of equipment and increased requirements for the speed of the circuit elements.

10, the accuracy of the measurement of the delay, the higher the frequency of the clock generator, the longer the analysis time of the correlation function, respectively, the increase in the analysis speed.

15 of the correlation curve leads to a decrease in the accuracy of the determined time delay.

The purpose of the invention is to increase the speed of the device and increase

20 measurement accuracy time delay.

b The goal is achieved by that / in the device containing the first shift register, the information

25 input of which is the first input of the device, a contact generator, the output of which is connected to the counter input of the divider frequency, the output of which is connected to the control inputs

30 of the first and second shift registers.

signal sample — frequency, the first input of which is the second input of the device, the second input combined with the input of the second shift register and connected to the output of the multiplexer,. the third input of the signal converter is connected to the output of the second shift register, a reversible counter, the lower-order outputs, which are connected to the corresponding setting inputs of the frequency divider, and the high-level outputs are connected to the control inputs of the multiplexer, a control unit, an arithmetic unit, and switches are entered according to the number of cells of the first shift register, the inputs of each switch are connected to the corresponding bit outputs of the corresponding cells of the first shift register, the outputs of the switches are connected The inputs of the control unit are connected to the first and second outputs of the signal-to-frequency converter and the output of the frequency divider, the first and second outputs of the control unit are connected to the corresponding inputs of the reversing counter, the third output is connected to the control inputs of the switches and the input of the arithmetic unit The other inputs of which are connected respectively to the outputs of the lower and higher bits of the reversible counter.

In addition, the control unit contains a trigger, two AND elements, three OR elements, two reversible counters and a counter, the inputs of the first reversible counter are respectively the first and second inputs of the control unit, the third input of which is the counter input, the output of which is connected to the first inputs the first and second elements are And, the second inputs of which are connected respectively to the first and second outputs of the trigger, the first and second inputs of which are combined respectively with the first and second inputs of the first OR element and Here, respectively, to the first and second outputs of the second reversible counter, which are respectively the first and second outputs of the control unit, the third output of which are the bit outputs of the second reversible counter, the first and second outputs of the first reversing counter, are connected to the first inputs of the second and third OR elements, the second inputs of which are connected respectively to the outputs of the first and second elements AND, the outputs of the second and third elements OR are connected to the corresponding inputs of the second reversible About the counter, the output of the first element OR is connected to the input of the zero setting of the counter.

Figure 1 shows the proposed device; Fig. 2 is a block diagram of a signal-frequency conversion unit; FIG. 3 is a control block diagram.

The first input of the device is connected to the input of the shift register 1, the output of each cell of the shift register, except the last one, is connected to the input of the next cell, the last n bits of each cell are connected via switches 2 to the corresponding inputs of multiplexer 3, and. where is the number of bits between the input of register 1 and the output of the cell with the number k; NV ;. - the number of bits between the input, register 1 and the output of the previous cell, where n, the number of bits of the cell with the number k, connected to the switch; P,. the number of bits of the previous register cell 1 connected to the switch.

The output of the multiplexer 3 is connected to the input of the signal-frequency converter 4 and the input of the shift register 5, the output of which is connected to another input of the converter 4. The third input of the converter 4 is connected to the second input of the device, the outputs of the converter 4 through the control unit 6 are connected to the counting inputs of the reversible counter 7 , the third output of block 6 is connected to the control inputs of the switches 2, and the input of the arithmetic unit 12, the output of the last bit from the group of lower bits 8 is connected to the counting input of the group of high bits 9 reverse 7 counter.

The outputs of the group of lower-order bits are connected to the control inputs of the frequency divider 10 and the inputs of the arithmetic unit. The input of the divider 10 is connected to the output of the clock generator 11, and the output to the control inputs of registers 1 and 5 and the input of block 6. The outputs of the higher bits 9 are connected to the control inputs of the multiplexer 3 and the inputs of the arithmetic unit 12.

Converter 4 contains an exclusive OR element 13, inverters 14 and elements 15 I. Reversible counters 16 and 17, counter 18, elements 19 and 20 AND, elements 21-23 OR and trigger 24 are used in the control unit.

The device works as follows.

The inputs of register 1 and converter 4 are supplied respectively to the reference and source signals, while the outputs of converter 4 generate signals whose frequencies are proportional to the values of the mutual correlation function of the reference and source signals in two children, corresponding to two-fold delay values - - gzhornog - signal.

The difference hour: one floor; -; x signals determines the direction of movement to the maximum point of the correlation function and is equal to zero when the delay of the reference signal corresponds to this maximum and, therefore, the time shift of the reference and original signals. When there is a mismatch, signals from converter 4 are received through block 6 on the reversible counter 7, causing a change in the frequency at the output of the divider 10. After changing the division factor, the block b during the Mj cycles prohibits the passage of signals from the converter 4 to the reversible counter 7. Signals from the block 6 arrive at the control of the switches 2, producing within N clock cycles by switching off taps in the corresponding cells of register 1, compensating for the time error resulting from the change of the clock frequency.

Converter 4 functions in accordance with the truth table.

So, for example, if N is 1000, and the period of the clock frequency F (at the output of divider 10) changes from 1 to 2 MKS with a discretization of 0.1 µs, when changing the period of the clock frequency from 1 to 1.1 MKS, the delay time between the reference and for each 10 clock cycles, the source signals are increased by one increment until the number of clock cycles equal to the number of the register register from which the reference signal is removed goes from the moment of switching the division factor of divider 10 (change F). To compensate for this time offset, every 10 clock cycles, block 6 switches the tap of register 1. using Koi wiyTaTopOB 2.

If all the low-order bits 8 are filled, the next pulse from the converter 4, which has passed the block b, resets the low-order bits and changes the state of the high-end bits 9 by one. This, in turn, causes the division factor of 10 changes from maximum to minimum. With multiplexer 3, the next register cell 1 is turned on, and the number of bits included is thus doubled.

Block b is again included in the time error compensation mode. If the movement continues

to extremum in the same direction (from left to right), the process is repeated. If the movement occurs in the opposite direction (from right to left), the sequence of events changes.

The operation of block b is as follows. Transducer 4 receives pulses at the inputs of a buffer reversible counter, at the output of which a transfer pulse appears, if the number of pulses arriving at the input

0 addition, exceeds the number of pulses arriving at the input of the subtraction, by a specified value. Similarly, a loan pulse appears at the other output, if the number of pulses at the input

5 subtracts more than the number of pulses at the input of the addition by the same amount. Through elements 21 and 22 HJJH, the pulses from the outputs of the buffer reversible counter are fed to the inputs of the reversible control counter, the state of the bits of which provides control of the switches 2 that carry out the switching of the required registers of the cells 1. When pulse occurs at one of the outputs ( no less than n

5 or no more), the reversible control counter performs a corresponding impact on the lower bits of the counter 8, leading to a change in the clock frequency F.

Once

Together with this, through the OR element 23, the counter is reset, which counts the s clock cycles of frequency Gd at the same time, while at its output successively after m clock cycles with p5 it is N./m pulses.

As soon as the counter is reset, a trigger is set up, which commits from the elements AND, the pulses from the output of the counter N./t come through

0 this circuit to the reversible control counter, producing a pulse count in the direction opposite to that which caused the appearance of the output pulse

5 (i.e., if a pulse appears at the output upon reaching the number n, the pulses are subtracted, and vice versa, if the output pulse appears at zero, the borrowing pulse,

0 pulses are added). Due to this, compensation of the time scale is made.

Delay time of the original signal

5 with respect to the reference is calculated by, the arithmetic unit of

(n,) t

60

where N. is the number of bits in k cells

register 1;

Claims (2)

k is the number recorded in the high bits 9; m is the division factor divided by l 10 (determined by the number recorded in bits 8); F is the frequency of the clock generator .tor; 11; PC is the number of the switched register cell 1, corresponds to the number coming from unit 6 to the control inputs of switch 2 and to the arithmetic unit 12. The discrete that determines the accuracy of the time measurement is equal to m / F and varies depending on the change in p. The invention makes it possible to increase the accuracy of the measurement of the delay time and increase the speed. The invention of the Correlation device for determining the delay, containing the first shift register, whose information input is the first input of the device, the clock generator, the output of which is connected to the counting input of the frequency divider, the output of which is connected to the control inputs of the first and second shift registers , the signal-frequency converter, the first input of which is the second input of the device, and the second input is combined with the input of the second shift register and connected to the output of the multiplexer, the third input is converted The transponder signal frequency is connected to the output of the second shift register, a reversible counter, the outputs of the lower bits of which are connected to the corresponding installation inputs of the frequency divider and the output of the higher bits are connected to the control inputs of the multiplexer, different from that; that, with the aim of increasing speed and increasing the accuracy of measuring the time delay, a control block, an arithmetic unit, and switches according to the number of cells have been introduced into it. the first shift register, the inputs of each switch are connected to the corresponding bits of the outputs of the corresponding cells of the first shift register, the switch outputs are connected to the corresponding multiplexer inputs, the inputs of the control unit are connected to the first and second outputs of the signal-frequency converter and the output of the frequency divider, first and second, respectively the second outputs of the control unit are connected to the corresponding inputs of the reversible counter, the third output of the control unit is connected to the control inputs of the switches and the input of the arithmetic unit, the other inputs of which are connected, respectively, to the outputs of the lower and higher digits of the reversible counter. 2. The device according to claim 1, wherein the control unit comprises a trigger, two AND elements, three OR elements, two reversible counters and a counter, the inputs of the first reversible counter are respectively the first and second inputs of the control unit, the third input of which is the input of the counter, the output of which is connected to the first inputs of the first and second elements And, the second inputs of which are connected respectively to the first and second outputs of the trigger, the first and second inputs of which are combined respectively with the first and second inputs ne The first element and OR are connected respectively to the first and second outputs of the second reversible counter, which are respectively the first and second outputs of the control unit, the third output of which is the bit outputs of the second reversible counter, the first and second outputs of the first reversible counter are connected to the first inputs of the second and the third element OR, the second inputs of which are connected respectively to the outputs of the first and second elements AND, the outputs of the second and third elements OR are connected with the corresponding the inputs of the second reversible counter, the output of the first element OR is connected to the input of the zero setting of the counter. Sources of information taken into account during the examination 1. USSR author's certificate No. 556450, cl. G 06 F 15/34, 1974. 2. USSR author's certificate number 636617, cl. G 06 F 15/34, 1976. To switches 2 Fig.Z