SU1114966A1 - Digital device for measuring frequency - Google Patents

Abstract

DIGITAL DEVICE FOR MEASURING FREQUENCY, containing the first driver, the input connected to the signal bus, the reference generator, the output connected to the input of the second driver, the first and second delay lines, the first and second counters, as well as the trigger, characterized in that increase the accuracy of measurements; a stroboscopic mixer, an amplifier-expander, an analog-digital converter, as well as two shift registers, six counters, four registers, a computing unit, two a subtractor unit, three code comparison units, a modulo two adder, a zero decoder, four AND elements, the first input of the stroboscopic mixer being connected to the output of the first driver and the counting inputs of the first, second, third, fourth, and fifth counters, and the second input the strobe mixer is connected to the output of the second driver, the control input of the analog-digital converter is connected to the control input of the first shift register, to the counting inputs of the sixth, seventh and eighth counters, to the first the first, second, and third element moves and through the first delay line to the control input of the second shift register and to the output of the reference Generator, and the digital outputs are connected to the information inputs of the first shift register, with the first information inputs of the calculator and the first the inputs of the first and second “block” comparison of the codes and the first block of you-C // read. the outputs of the third block of code comparison connected to the first outputs, the second inputs of which are connected to the outputs of the zero decoder and to the first outputs of the second calculator, the second output of the second subtraction unit are connected to the first input of the modulo two, with the first control inputs of the second and Third of the registers and with information inputs of the fourth register, the first inputs of the second subtraction unit are combined with the first information inputs of the second and third registers, the second inputs of the first block are read and a first output of the first shift register, a second input - to the second information inputs of the second and third registers and second outputs of the first shift register, the output of the second shift register fed logical level 1, its first

Description

the output is combined with the first control inputs of the first, third and sixth counters, the second output with the first control inputs of the second, fourth, seventh counters and the second control input of the third counter, and the third with the second inputs of the second and third elements And, third the inputs of which are connected respectively to the direct and inverse outputs of the fourth element I, the first and second inputs of which are connected to the inverse outputs of the trigger and the decoder zero, respectively, and the third to the output of the third comparison unit c, the output of the second element I is combined with the control input of the fourth register, with the third control input of the third counter, with the first control input of the nepBOto register, with the second control inputs of the second and third registers, the first, sixth counter and with the first control the inputs of the fifth and eighth counters and with, 5-trigger input, the output of the third element And is combined with a fourth control input of the third counter, with the third control inputs of the first and sixth counters and with the second control inputs of the second the fourth and seventh counters, while the outputs of the latter are connected to the information inputs of the first, third and sixth meters respectively, which are connected to the information inputs of the fifth counter, the first register and the eighth counter, respectively, the outputs of the latter are connected to the second, third and fourth information inputs of the computing unit, the fifth information inputs of which are connected to the outputs of the second register and to the second inputs of the first code comparison block, and the sixth information These inputs are to the outputs of the third register and to the second inputs of the second code comparison unit, the output of the first element I connected to the second input, to the third input of which the output of the first code comparison unit is connected, to the fourth one the inverse output of the modulo two, the second input of which is connected with the output of the fourth register, and the combined input of the first element I connected the combined direct output of the trigger and the second control inputs of the fifth and the eighth counters, the third control inputs of which are combined with the R input of the trigger, with the BTopbjM control input of the first register, with the control input of the computation unit and through the second delay line connected to the output of the first element I.

The invention relates to the field of measuring and pulse technology - and can be used to measure the frequency of periodic electrical signals,

Known digital frequency meter containing a reference oscillator, pulse shaper, coincidence circuits, triggers, keys and counters. The device is based on counting the number of periods of the unknown and reference frequencies in the merio interval, the boundaries of which are formed by the nearest coincidence pulses of the compared frequencies D1

However, this device has a large measurement error due to the fact that the compared sequences of the drivers have finite duration at the outputs of the drivers, as a result of which the packages of Impulses of coincidences are realized at the output of the coincidence circuits, and the measured interval can be formed by the closest matches of the coincidences, the input in one package.

Closest to the invention is a digital device for comparing frequencies, containing the first driver, the input connected to the signal bus with an unknown frequency, the reference oscillator, the output connected to the second driver, the first and. the second delay line, the first 3111 and the second counters, the trigger, as well as the element of coincidence, the keys and the trigger1) s. This device has the possibility of obtaining measurement errors due to the formation of a measuring interval for the nearest coincidence pulses included in one packet 2. ; However, the known device also has a frequency measurement error caused by the fact that the coincidence pulses forming the boundaries of the measurement interval may result from an inaccurate alignment of the generated pulses of the reference oscillator and the signal with an unknown frequency. As a result, in the general case, the integer interval does not fit the integer number of periods of one of the matched sequences, while the measurement result is determined by the integer number. . The aim of the invention is to increase the measurement accuracy. The goal is achieved by the fact that a digital frequency measuring device containing a first driver, an input connected to the signal bus, a reference oscillator, an output connected to the input of the second driver, the first and second delay lines, the first and second counters, as well as a trigger, are connected in series stroboscopic mixer, amplifier-expander, analog-digital converter, as well as two shift registers, six counters, register register, deduction unit, two subtraction units, three units and codes, an adder modulo two, a zero decoder, four AND elements, the first input of the stroboscopic mixer connected to the output of the first driver and counting inputs of the first, second, third, fourth and fifth counters, and the second input of the stroboscopic mixture of bodies is connected to the output of the second driver, the control input of the analog-digital converter is connected to the control input of the first shift register, to the counting inputs of the sixth, seventh and eighth counters, to the first inputs of the first, second and third elements Both through the first delay line to the control input of the second shift register and to the output of the reference generator, and the digital outputs are connected to the information inputs of the first shift register, with the first information inputs of the computation unit and with the first inputs of the first and second code comparison blocks and the first a subtraction unit, outputs connected to the first inputs of the third block of comparison of codes, the second inputs of which are connected to the inputs of the decoder zero and to the first outputs of the second subtraction unit, the second output of the second block in subtracting coupled to the first input of the adder of modulo two, the gate to the first inputs of the second and third registers and informatsionnm input of the fourth register, the first input of the second subtracting unit combined with the first informatsionny-. the inputs of the second and third registers, the second inputs of the first subtraction unit and the first outputs of the first shift register, and the second inputs with the second information inputs of the second and third registers and the second outputs of the first shift register, while the logical 1 is input to the second shift register, its first output is combined with the first control inputs of the first, third and sixth meters, the second output of the first control inputs of the second, fourth, and seventh meters and the second control input of the third counter, and the third - with the second inputs of the second and third elements And, the third inputs of which are connected respectively to the direct and inverse outputs of the fourth element And, the first and second inputs of which are connected to the inverse outputs of the trigger and decoder zero, respectively, and the third with the output of the third the code comparison unit, the output of the second element I is combined with the control input of the fourth register, with the third control input of the third counter, with the first control input of the first register, with the second control input and second and third registers, first, sixth counters and first control inputs of the fifth and eighth counters and with 5 trigger inputs, the output of the third element I is combined with the fourth control input of the third counter, with the third control inputs of the first and sixth counters and the second control inputs of the second, fourth and seventh counters, while the outputs of the 511114 glacier are connected to the information inputs of the first, third and sixth meters, respectively, which are connected to the information inputs from responsibly the fifth counter, the first register and the eighth counter, the outputs of the latter are connected respectively to the second, third and fourth information inputs of the computing unit, the fifth information inputs of which are connected to the outputs of the second register and to the second inputs of the first comparison code block, and the sixth information inputs - to the outputs of the third register and to the second inputs of the second block of code comparison, the output connected to the second input of the first element I, to the third input of which the output of the first block is connected codes, to the fourth - the inverse output of the adder on two two, the second input of which is connected to the output of the fourth pegister, and the combined first output of the trigger and the second controlling inputs of the fifth and eighth counters are connected to the fifth input of the first element And, the third control The inputs of which are combined with the R input of the trigger, with the second control input of the first register, with the control input of the calculation unit and through the second delay line are connected to the output of the first element I. In FIG. 1 shows a block diagram of the device; in fig. 2 shows the times for the operation diagram of a digital device for measuring frequency, explaining the sequence of operations and the interaction of the blocks. The digital device for measuring the frequency contains (Fig. 1) the first driver 1, the reference generator 2, the second driver 3, the stroboscopic mixer 4, the amplifier expander 5, the converter 6 analog-digital (ADC), the first delay line 7, the first shift register 8, the second shift register 9, first eighth counters 10-17, respectively, first register 18, second register 19 first subtraction unit 20, third register 21, computation block 22, fourth register 23, second subtraction unit 24, first block 25 of code comparison, adder 26 modulo two, second and the third blocks 27 and 28 of the code comparison, the depotfrrator 29 zero, the first element AND 30, the trigger 31, the second element AND 32, the second delay line 33, the third and fourth elements And 34 and 35. The driver 1 is connected to the signal bus. The output of the generator 2 is connected to the input of the imager 3. The first input of the stroboscopic mixer 4 is connected to the output of the imager 1 and to the counting inputs of counters 10-14, the second input - with the output of the imager 3, and the output through the amplifier A1Sh 6. The control input of the ADC 6 is connected to the control input of the first shift register 8, to the counting inputs of counters 15-17, to the first inputs of the And elements 30, 32 and 34 and through the delay line 7 to the control input of the second shift register 9 and to the output generator 2, and digital inputs - to inform on the first information inputs of the computing unit 22 and to the first inputs of the first and second blocks 25 and 27 of the code comparison and the first subtraction unit 20. The outputs of the latter are connected to the first inputs of the third block 28 of the code comparison, the second inputs of which are connected to the inputs of the decoder 29 zero and to the first outputs of the second block 24 of the subtraction. The second output of block 24 is connected to the first input of the adder 26 modulo two, with the first control inputs of registers 19 and 21 and with the information input of register 23. The first inputs of subtractor 24 are combined with the second information inputs of subtractor 20 and with first outputs of register 8 shift, and the second inputs - with the second information inputs of the registers 19, 21 and the second outputs of the register 8 shift. At the same time, logic level 1 is applied to the input of shift register 9. Its first code is combined with the first control inputs of counters 10, 12 and 15, the second output with the first control inputs of counters 11, 13, and 16 with the second control input of counter 12, and the third - with the second inputs of the elements 32 and 34, the third inputs of which are connected respectively to the direct and inverse outputs of the element 35, the first and second inputs of which are connected to the inverse outputs respectively of the trigger 31 and the decoder 29 zero, and the third one codes. You711

the element code 32 is combined with the control input of the register 23, with the third control input of the counter 12, with the second, control inputs of the registers 18, 19 and 21, the counters 10, 15 and with the first control inputs of the counters 14 and 17, and with 5 trigger input 31. Element 34 output is combined with fourth control input of counter 12, third control inputs of counters 10 and 15, and second control inputs of counters 11, 13 and 16, - the outputs of the latter are connected to information inputs counters, respectively, 10, 12 and 15, which outputs are connected to the information th inputs, respectively, of the counter 14, register 18 and counter 17, the outputs of which are connected respectively to the second, third and fourth information inputs of the computing unit 22, the fifth information inputs of which are connected to the outputs of the register 19 and the second inputs of the block 25 compared to the codes, and the sixth - to the outputs of the register 21 and to the second inputs of the code comparison unit 27, the output of the And 30 element connected to the second input. To the third input of the I 30 element, the output of the code comparison unit 25 is connected, to the fourth - the inverse output of the modulo 26 , the second input of which is connected to the output of register 23, the combined direct output of trigger 31 and the second control inputs of counters 14 and 17, the third control inputs of which are combined with the R input of trigger 31, are connected to the second input of element I 30, with the second control The register 18 input and the control input of the computation unit 22 and through the delay line 33 are connected to the output of the element 30.

The device works as follows.

 In the initial state, the equipment of the ADC 6, shift registers 8 and 9, counters 10-17, registers 18, 19, 21, 23 and block 22 of calculations, trigger 31 are set to O. At the input of the imaging unit 1, a signal is transmitted with an unknown frequency. Shaper 1 generates a test sequence of pulses that have linear segments on the fronts and which follow with the frequency of the signal under study (Fig. 25). These pulses arrive at the first input of the stroboscopic mixer 4. On

AT

the second input of the latter through the strobe pulse shaper 3 pulses of the generator 2 (Fig. 2 q), sampling from the output of the mixer 4 (Fig. 2))

amplified and expanded to the required duration by the amplifier-expander 5 and fed to the input of the ADC 6, which on the leading edge of each pulse of the generator 2 performs

conversion of the amplitude of the sample into a digital code. This code enters the information inputs of the shift register 8 and is written into its first bits. Write and shift are performed.

on the falling edge of each pulse of the generator 2. Line 7 is necessary to compensate for the delay in the driver 3, the mixer 4, the amplifier-expander 5, as well as in the shift register 9.

The device selects the first and second samples — the two following subsections of the linear edge portion of the extended signal, for which it continuously analyzes the three following subsections.

sampling and, and and ut. A sample code with amplitude and is stored in the second bits of shift register 8, code O in the first, it code is at the output of the ADC 6. The conditions

Gli, whether rAebu,,,. ,about

This is a sign that the samples with amplitudes U, U lie on the linear edge of the extended signal. Sequential analysis of incoming samples allows finding samples that satisfy conditions (1) that are taken as the first and second samples with amplitudes U and U, respectively, and the first one is always taken from the samples whose amplitude is less than, t. e.

Gi and

if u-iu; u, .u

Gi and

if u, u

Then the device switches to the third sample selection mode with amplitude Uj, if 55 j is taken as a sample lying on the same front as the first and second, but the next extended signal, the amplitude of which satisfies the condition 1 U ,,. By counting the number of Nr Q periods of the reference and the number of NX, of the periods of the studied sequence in the measuring interval, the first and third samples are chosen as the boundaries of which, and also calculating the number N of the periods of the studied sequence in the interval between the first and second samples, the device calculates the Tj period following the pulses of the studied sequence according to the formula (,, С °, ecftMN.i -: j--, к - ::. where TQ is the period of following pulses of the reference generator 2. After that, the device automatically switches to a new measurement cycle, i.e. selects new first and second samples, while analyzing the amplitudes of incoming samples to fulfill conditions (1) is carried out in the selection mode of the third sample in the previous measurement cycle, and also selects a new third sample. Thus, the described operations are repeated cyclically The results of a series of measurements of T can be used for the accumulation and statistical averaging of the measured value Tu, which will make it possible to further improve the accuracy of measurements. Let us consider in more detail the operation of the bloi of the proposed device. On the leading edge of the first after the moment of switching on the pulse, the generator 2 in the first discharge of register 9 shift is entered 1. At the same time, the first control inputs of counters 10, 12, and 15 receive a signal enabling the counting. On the leading edge of the second impulse of the generator 2 1 appears also in the second discharge of the shift register 9. At the same time, the counter 610 11, 1.3, 16 is allowed and the counter 12 is prohibited, in which the calculated number of pulses of the studied sequence in the time interval between the first and second pulses of the generator 2 is calculated. To obtain a correct measurement result, you need to choose the following two q samples lying on the linear portion of the front of the extended signal. This operation is carried out by register 8, blocks 2b, 24, 28. Decoder 29, trigger 31, elements 32, 34 and 35. After the third and all subsequent generator pulses 2, there are 1 in all three bits of shift register 9, as a result of which At the inputs of elements 32 and 34, a potential appears that permits the analysis of the amplitude code of three consecutive samples — C recorded in the second bits of shift register 8, U. recorded in the first register bits 8. shift and Jt are the amplitudes of the current sample at the output of the ADC 6. At the first outputs of subtractor 24, there is a difference all the time (1 and - and, at its second output - the sign of the difference uU, and at the outputs of block 20, HocTbi.U2 UT is generated and in case the conditions (1) are not fulfilled, the generator 2 is overwritten by the contents of counter 11 e, counter 10, the contents of counter 13, counter 1.2, and counter 16 - into counter 15, since it becomes obvious that the sample with amplitude U does not lie on the linear portion of the front of the expanded signal, and the values calculated by the sc The sensors 10, 12 and 15 will not be required for calculations. After overwriting (on the falling edge of the generator 2 pulse), the counters 11, 13 and 16 are set to O and start working from the beginning. Similar actions are performed if conditions (1) are fulfilled, but the device is already in the third sample selection mode, i.e. the first and second samples with amplitudes and, and and are selected and the device waits for samples with amplitudes that satisfy the condition. (2) and the extended signal lying on the same front, That first and second sample. Only if conditions (1) are fulfilled and there is no indication of the third sample selection mode, i.e. if trigger 31 is set to O, on the front / front of the signal from the output element. And 32, the information days are rewritten from counters 10, 12 and 15, respectively, to counter 14, register 18 and to counter 17, trigger 31 is set to 1, which is a sign of the device operating in the third sampling mode. At the same time, the CHR from the direct output of the trigger 31 enables the operation of the counters 14 and 17. On the falling edge of the signal from the output of element 32, the counters 10, 12 and 15 are reset. In addition, the sign 23 is written to the sign of the difference Ml). The same sign controls the recording of information in registers 19 and 21. If iSiLli O, then in the register 19 the sampling code is written from the second bits of the shift register 8, and in the register 21 - from the first. If, however, -c 0, then in the register 19 the sample code from the first bits of the shift register 8 is written, and in the register 21 - from the second. Register 19 is the storage unit of the first sample with amplitude Ui, register 21 is the storage unit of the second sample with amplitude q 2 In the selection mode of the third sample, the following actions are additionally performed. For each pulse of generator 2, it is checked whether the current sample lies with an amplitude, the code of which is present at the moment. The output of the A / D converter is 6, on the same front of the extended signal as the first and second samples, for which the adder 26 checks whether the signs are 6, U (which is stored in register 23) and what is present at the second output block 24; whether 6612 UT satisfies condition (2), which is checked by blocks 25, 27 of the code comparison and AND 30. If the current sample lies on the same front of the extended signal as the first and second samples, or its amplitude does not satisfy condition (2), the device remains in the third sample selection mode. If the current sample satisfies the requirements for the third sample, then the signal from the output of element I 30 through delay line 33 (with Sc, where t c is the pulse width of generator 2, since the counters 10-17 count on the falling edge at their inputs pulses), turns off the counter 14, in which the number NX is calculated, turns off the counter 7, in which the number Q is calculated, calculates the information from the registers 21 in the calculation block 22 (code Uj) 19 (U code), 18 (number Hx ) counters 14 and 17, code U | - 11 from the output of the ADC 6, sets the trigger 31 to O, i.e. removes the sign of the choice of the third sample and resolves the transition to the next cycle of i-. measurements, and also includes a block of 22 calculations, which is calculated from the initial data obtained in this cycle as Tu. The maximum error value can reach the value of C K2; M-J) The measurement accuracy of the proposed device as compared with the known device can be increased to the value determined by this ratio.

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Claims (1)

A DIGITAL DEVICE FOR MEASURING FREQUENCY, containing the first driver, connected to the signal bus by an input, a reference generator connected to the input of the second driver, the first and second delay lines, the first and second counters, • and a trigger, characterized in that, for the purpose of to increase the accuracy of measurements, a stroboscopic mixer, an amplifier-expander, an analog-to-digital converter, as well as two shift registers, six counters, four registers, • a calculation unit, two blocks are introduced into it; and subtraction, three blocks for comparing codes, an adder modulo two, a zero decoder, four AND elements, the first input of the stroboscopic mixer connected to the output of the first shaper and to the counting inputs of the first, second, third, fourth and fifth counters, and the second input of the stroboscopic the mixer is connected to the output of the second driver, the control input of the analog-to-digital converter is connected to the control input of the first shift register, to the counting inputs of the sixth, seventh and eighth counters, to the first inputs of the first of the first, second and third elements of AND and the calculation unit and from the first and second block of codes and the first output block connected to via the first delay line to the control input of the second shift register and to the output of the reference Generator, and digital outputs are connected to the information inputs of the first shift register , with the first information inputs and read comparison inputs. the first outputs of the third block of code comparison, the second inputs of which are connected to the outputs of the zero decoder and ~ to the first outputs of the second subtraction unit, the second output of the second subtraction unit is connected to the first input ί of the adder modulo two, with the first control the inputs of the second and third registers and with the information inputs of the fourth register, the first inputs of the second block of subtraction are combined with the first information inputs of the second and third registers, the second inputs of the first block of subtraction and with the first outputs of the first about the shift register, and the second inputs with the second information inputs of the second and third registers and the second outputs of the first shift register, while the logic level is applied to the output of the second shift register ”1, its first output is combined with the first control inputs of the first, third and the sixth counter, the second output with the first control inputs of the second, fourth, seventh counters and with the second control input of the third counter, and the third with the second inputs of the second and third elements And, the third inputs of which are connected respectively correspondingly to the direct and inverse outputs of the fourth AND element, the first and * second inputs of which are connected to the inverse outputs of the trigger and the zero decoder, respectively, and the third to the output of the third code comparison unit, the output of the second AND element combined with the control input of the fourth register, with the third control input of the third counter, with the first control input of the first register, with the second control inputs of the second and third re-; the histors of the first, sixth counters and with the first control inputs of the fifth and eighth counters and with a 5 trigger input, the output of the third AND element is combined with the fourth control input of the third counter, with the third control inputs of the first and sixth counters and with the second control inputs of the second, the fourth and seventh counters, while the outputs of the latter are connected to the information inputs of the first, third and sixth counters, respectively, which are connected to the information inputs of the fifth counter by outputs a, the first register and the eighth counter, the outputs of the latter are connected respectively to. the second, third and fourth information inputs of the computation unit, the fifth information inputs of which are connected to the outputs of the second register and the second inputs of the first code comparison unit, and the sixth information inputs - to the outputs of the third register and the second inputs of the second code comparison unit, the output connected to the second the input of the first element And, to the third input of which the output of the first block of code comparison is connected, to the fourth - the inverse output of the adder modulo two, the second input of which is connected to the output of the fourth p an integer, and the fifth direct input of the trigger and the second control inputs of the fifth and eighth counters are connected to the fifth input of the first element And, the third control inputs of which are combined with the R-input of the trigger, with the second control input of the first register, with the control input of the calculation unit and through the second line delays are connected to the output of the first element I.