SU883914A1 - Correlation device for determination of delay time - Google Patents

Description

Noah curve is oscillatory, i.e. has several extremes. To determine the delay time, it is necessary to find the maximum extremum of the correlation function.

The disadvantage of this device is the possibility of determining the delay time by a minor extremum, respectively, the measurement accuracy is low, if there are several emissions of the correlation function in the area under study.

The purpose of the invention is to improve the accuracy of determining the delay time.

The goal is achieved by the fact that a correlation device for measuring the delay contains the first shift register, whose information input is the first input of the device, and the outputs of the first shift register are connected to the corresponding information inputs of the first multiplexer, the clock generator, the output of which is connected to the count input of the divider. frequency, the output of which is connected to the control inputs of the first and second shift registers and with the clock input of the first display unit, voltage-h converter The first input of which is the second input of the device, the second input is connected to the output of the multiplexer and the input of the second shift register, the third input of the voltage-frequency converter is connected to the output of the second shift register, the control input of the multiplexer is connected to the output of the CHBtJoro counter, the first and second the inverter outputs the frequency is connected respectively to the first and second inputs of the reversible counter, the outputs of the higher bits of which are connected to the corresponding information inputs of the display unit , the low-order outputs are connected to the control inputs of the frequency divider, the third and fourth shift registers are introduced, the second multiplexer, the second voltage-frequency converter often, the second reversible counter, the second frequency divider, the second display unit, the comparator, two integrators, two elements AND, comparison unit, the inputs of which are connected respectively to the outputs of the first and second reversible counters, the output of the comparison unit is connected to the first inputs of the first and second elements AND, the output of the first element AND connected to the input the addition of the first reversible counter, the output of the second element I is to the subtraction input of the second reversible counter, the second inputs of the elements AND are connected respectively to the first and second outputs of the comparator, the inputs of which are connected respectively to the outputs of the first and second integrators, the input of the first

the integrator is connected to the second output of the first voltage converter; the input of the second integrator is connected to the first output of the second voltage-frequency converter, the first input of which is connected to the second input of the device; the input of the third shift register is connected to the first input of the device; the outputs of the third register are connected to the corresponding information inputs The second multiplexer, the control input of the second multiplexer is connected to the output of the second reversible counter, the outputs of 1-1 zadshih bits connected to the installation inputs of the second frequency divider, whose information input is connected to the clock generator output, and the output is connected to the clock input of the second display unit and to the control inputs of the third and fourth shift registers, the output of the second multiplexer is connected to the input of the fourth shift register and with the second input the second voltage-frequency converter, the third input of which is connected to the output of the fourth shift register, the first and second outputs of the voltage-frequency converter are connected corresponding It is responsible for the control inputs of the reversible counter.

FIG. 1 is a diagram of the device according to FIG. 2 shows the dependence of the clock frequency Fg and the indication frequency on the delay value; in fig. 3 - the form of the correlation curve R (t) and the sequence of operation of the device when moving to the maximum extremum.

The device contains the first and second channels 1 and 2 of determining the extremum of the correlation function, the first and third shift registers 3, multiplexers 4, voltage-frequency converters 5, the second and fourth shift registers b, reversible counters 7, low bits 8 counters, older bits 9 counters, frequency dividers 10, clock generator 11) indication unit 12 comparison unit 13, elements 14 and 15, integrators 16 and 17, comparator 18.

In the proposed device, the first input is connected to the first input of channel 1 of the extremum determination and the first input of channel 2. The definition of the extremum, the second input of the device is connected to the second inputs of channels 1 and 2, respectively.

The first input in each channel for determining the extremum (the reference signal circuit is connected to the input of the shift register 3, the output of each cell of the shift register 3, except the last one, is connected to the input of the next cell, the output of each cell is also connected to the input of the multiplexer 4, and Dov

between the input of the register 3 and the output (cells with the number of bits between the register input and the output of the pre-rotating cell; the output of multiplexer 4 is connected to the input of the converter and the shift register 6, the output of which is connected to another input of the converter 5, the third output of which is connected to the second input of the channel , the outputs of the converter 5 are connected to the counting inputs of the reversible counter 7, the output of the last bit from the group of the lower bits 8 is connected to the counting inputs of the group of the higher bits 9 of the reverse counter, the outputs of the younger times The 8 ports of the counter 7 are connected to the installation inputs of the frequency divider 10, the input of which is connected to the output of the clock generator 11, and the output to the control inputs of the shift registers 3 and 6 and the input of the display unit 12, the outputs of the higher bits 9 of the reversible counter 7 are connected to the unit the indication 12 and the control inputs of the multiplexer 4, in addition, the higher bits of the reversing counters 7 of each channel are connected to the corresponding inputs of the comparison unit 13, the output of which is connected to the first inputs of the elements 14 and 15, the first output converter 5 of channel 1 through the integrator 16, and the second output of converter 5 of channel 2 through the integrator 17 is connected to the corresponding inputs of the comparator 18, one output of which is connected to the input of the And 14 element, and the second to the input of the And 15 element, the output of the And 14 element is connected with the first input (the input of the addition of the reversing counter 7 of channel 1, and the output of the element 15) with the second input (the input of the subtraction of the reversing counter 7 of the channel 2.

The device works as follows.

With commissioning, the initial installation of the reversing counter 7 of channel 1 is performed, the minimum possible delay value, the number recorded in the upper 9 of reversing counter 7 switches from the register 3 the corresponding cell, in the same way the maximum possible delay value is set in channel 2. The inputs of the registers 3 of both channels and transducers 5 are supplied respectively to the reference and source signals. At the same time, the outputs of the converter 5 in the Ks1cd channel generate signals whose frequencies are proportional to the values of the mutual correlation function of the reference and source signals at two points corresponding to two slightly different values of the reference delay (the number of bits

shift register 6). The difference of these frequencies of the signals determines the direction of movement to the point of extremum and is equal to zero when the delay corresponds to the position of the extremum. When the meter mismatch, the counter state changes, causing a change in the frequency at the output of the divider 10. If all the lower bits 8 of the counters 7 become full, which corresponds to the maximum division frequency of the generator 11, then the next pulse at the input of the reversing counter 7 resets the lower bits of the counter and changes by one the state of the high-order bits 9. This, in

5, in turn, results in the division factor of divider 10 becoming minimal; using multiplexer 4, the next cell of shift register 3 is turned on, and

The 0 bits included are thus doubled. If the movement continues to the extremum in the same direction, the process is repeated. If the motion occurs in the opposite direction, then the sequence of events changes accordingly.

In parallel with the analysis of the correlation functions of the voltage-frequency converter 5, the ordinate correlation is integrated: the functions at the studied points are integrated by integrators 16 and 17. In the comparator 18, the integration results are compared, and a control signal is generated at its corresponding output, passing through the corresponding element AND 14 or 15 and the reversible counter 7 to the input of the addition in the first channel or on

0 input subtraction in the second channel, the caNbiM will initiate the convergence of time points analyzed in the first and second channels. Elements 14 and 15 are open for passing signals from the comparator until the 5 results are equal in the upper bits of 9 reversible counters 7 of both channels, after which both channels are switched to the autonomous mode for determining the maximum correlation function.

In the display unit (Fig. 2), a frequency is generated that is proportional to the delay value, while the clocking frequency of register 3, equal to 5 at the frequency at the output of divider 10, changes only twice, remaining high at any values of the measured delay.

The sequence of the device operation while moving to the maximum of the correction function (maximum extremum) is reflected in FIG. 3

The initial analysis corresponds to the moment when the first channel is analyzed (W is the extremum at point A, and the second

five

the extremum channel, at point B. Since the extremum at point B is less than the extremum at point A, the control signal from comparator 18 through element 15 enters the reversible counter of the second channel, causing the analyzed section to shift to the left (1 marj. Since the comparator 18 generates a control signal according to the function values at the extreme points Ajj and, in the first step, respectively, point movement is shown. At the c / point point, the correlation function value is equal to the function value at the Al point, from this moment the comparator stops generating a control signal The ent And 15, respectively, the second channel switches to the autonomous extremum search mode, gradually moving to a point. As soon as the second channel goes to the analysis to the left of point b1, the value of the correlation function becomes higher than that fixed by the integrator 16, accordingly the comparator 18 switches the control signal to another exit, shift the analysis point of the first channel from the extremum A /) to the right. Thus, at the second step, the analyzed points in the two channels simultaneously move towards each other, until the second channel stops to fix the extremum at the Bj point. The SECOND channel will be fixed at the extremum at point B-j until the number in integrator 16 reaches the number stored in integrator 17. (point. From this moment, the third step begins, the first channel goes into autonomous maximum search mode, and the second one moves towards each other.

At the moment of equality of numbers (the same cell in the registers 3 of the first and second channels) in the higher bits 9 counters 7 of both channels, the comparison unit 13 generates a signal covering the elements 14 and 15, both channels go to the autonomous maximum search mode correlating function.

The known device, when analyzing the correlation function (Fig. 3), can stop at any of the extremes, respectively, producing an erroneous result,

The proposed two-channel device, with additional AND elements, a comparison circuit and a comparator, allows the channel to be compressed from the analysis of intermediate extremum, when the adjacent channel proceeds to the analysis of the section where the value of the correlation function exceeds the value of this intermediate extremum.

In this way, errors in determining the delay times due to the fixation of intermediate extremes are avoided, since it can be concluded that the device has a positive effect.

Claims (2)

Invention Formula A correlation device for determining the delay time, containing the first shift register, the information input of which is the first input of the device, the outputs of the first shift register are connected to the corresponding information input of the first multiplexer, the clock generator, the output of which is connected to the count input of the frequency divider, the output of which is connected to the control inputs of the first and second shift registers and with the clock input of the first display unit, the voltage-frequency converter, the first input of which is The second input of the device, the second input is connected to the output of the multiplexer and to the input of the second shift register, the third input of the voltage-frequency diverter is connected to the output of the second shift register, the control of the first multiplexer is connected to the output of the first reversible counter, the first and second the outputs of the voltage-frequency converter are connected respectively to the first and second inputs of the reversible counter, the outputs of the higher bits of which are connected to the corresponding information inputs of the first block ind The outputs and the lower ranks are connected to the control inputs of the divider source, characterized in that, in order to improve the accuracy of determining the delay time, the third and fourth shift registers, the second multiplexer, the second voltage converter, the second reversible counter, are introduced into the correlation device, the second frequency divider, the second display unit, the comparator, two integrators, two AND elements and a comparison unit, whose inputs are connected respectively to the outputs of the first and second reversible counters, output the comparison unit is connected to the first inputs of the first and second elements I, the output of the first element I is connected to the input of the first reversible counter, and the output of the second element I to the subtraction input of the second reversible counter, the second inputs of the elements AND, are connected respectively to the first and second outputs of the comparator The BXOJKI of which connects respectively to the outputs of the first and Btoporo integrators, the input of the first integrator is connected to the second output of the first voltage-frequency converter, the input of the second integrator is connected En "the first output of the second voltage-frequency converter, the first input of which is connected to the second input of the device, the input of the third shift register is connected to the first input of the device, the outputs of the third register are connected to the corresponding information inputs of the second multiplexer, the control input of the SECOND multiplexer is connected to the output of the second reverse the counter, the outputs of the lower bits of which are connected to the installation inputs of the second frequency divider, the information input of which is connected to the output clock generator, and the output is connected to the clock input of the second display unit and to the control inputs of the third and fourth shift registers, the output of the second multiplexer is connected to the input of the fourth shift register and the second input of the second voltage-frequency converter, the third input of which is connected to the output of the fourth shift register, the first and second outputs of the voltage converter, the frequency is connected to the control inputs of the reversible counter. Sources of information taken into account in the examination 1. The author's certificate of the USSR 466453, cl. G 06 F 15/336, 1972. 2. USSR author's certificate number 636617, cl. G 06 F 15/336, 1976 (prototype).