SU1688259A1 - Device foe convolution calculating - Google Patents

Abstract

The invention relates to computing and can be used in digital processing systems for radar, video, seismic, sonar and other signals. The purpose of the invention is to enhance the functionality by calculating the autocorrelation function. The device contains multiplier groups, input data registers, inverters, triggers, synchronizer, mode triggers, four-input multiplexers, AND elements, operand registers, multipliers, adders of the first group, adders of the second group, sum registers, two-input multiplexers, registers. 4 il.

Description

The invention relates to computing technology, is intended to calculate a correlation function and a digital filtering procedure, and can be used in digital signal processing systems.

The aim of the invention is to enhance the functionality of the device by calculating the autocorrelation function on the device.

FIG. 1-3 shows a block diagram of the device; 4 shows an example of the implementation of a synchronizer function diagram.

The device (Fig. 1-3) contains a group of 1 multipliers, registers of 2 input data, inverters 3.1, triggers 4.1, synchronizer 5, triggers 6.1 modes, four-input multiplexers 7.1, inputs 8.1 and 8.2 set the device mode, elements And 9.1,

operand registers 10.1 (1 1, Yu, information input 11, group of 12 multipliers, group of 13 adders, group of 14 adders, registers of sums 15.1, output of device 16, two-input multiplexers 17 and 18, groups of 19 and 20 registers, inputs 21 and 22 coefficients of impulse response.

The synchronizer (FIG. 4), implemented for N 4, contains a counter 21 modulo N, a decoder 22, an AND-NE element 23, an AND 24 element, triggers 25 and 26, a demultiplexer 27, an inverter 28, and a clock pulse generator 29.

The operation of the device when calculating the correlation of the input array.

The device evaluates the following expression:

NI;

R (K) 2C X n +, K O, N-1,

)

About 00

oo ate

with

de with AND, R (K)

For the first form of braz:

X (0)

X (3)

input array blocks

rpchmrrnosti N;

where C is the remainder of dividing

3n h b;

The kth count of the correlation function.

4 expression (1) in the matrix can be written as follows

X (3)

X (2)

X (0)

X (3)

R (0) R (3)

R (2)

Ed)

(2)

We assume that the operands in registers 2.1, 15.i, YuL, 6.1, 19. g, 20-.i are taken on the leading edge of the clock (for simplicity, the synchronization of registers 19.1 and 20.1 are not shown), the calculation mode for the correlation of the input array corresponds to a value of 11 at inputs 8.1 and 8.2 of synchronizer 5.

For the purpose of identical presentation of the modules, the second input of the adder 14.N / 2 is connected to the logical zero bus, in order to limit the number of inputs and preserve the functionality of the module, the sync signal inverter 3.1 is inserted into each module. From the output of the clock generator, a sync signal is received in the form of a meander.

Using the example of N 4, we consider the operation of the device when calculating the correlation of the input array.

First beat In the initial state, both the 6.1 and 4.1 triggers are written in zeros, and the operand X (0) is present at the input 11 of the device. The control input of the multiplexer 17 from the fifth output of the Synchronizer 5 is fed to a single value, and the control input of the multiplexer 18 is supplied with a zero value from the sixth output of the synchronizer 5. A positive sync pulse operand) is written to the register 2.1, and a positive differential inverted clock pulse - in the register 19.1. Informational Input Trigger 4.2 receives a single value from the second output of synchronizer 5, and informational input of Trigger 6.2 receives a single value from the third output, since the leading edge of the sync pulse arrives earlier than the change occurs at the information input of triggers, then the state of the trigger 6.2 and 4.2 le is changed

0

five

0

five

0

five

0

45

0

55

state does not change and trigger 6.1 and 4.1.

Further operation of the device is carried out in a similar manner in seven cycles.

If linear correlation is to be calculated, the corresponding number of input samples is filled with Zeros.

When implementing a digital filtering procedure, the device calculates the filter output samples in accordance with the expression VH

X (K) 2a (K - n) h (n), (3) p o

where h (n) - coefficients of the impulse response of the filter1, and (n) - samples of the output signal. The device can perform digital filtering with two different impulse response. The first digital filtering mode corresponds to the control signals 10 at inputs 8.1 and 8.2, respectively. The coefficients of the first impulse response are fed to the inputs 21.1 accordingly and do not change during the calculation. The second digital filtering mode corresponds to code 01 at the control inputs 8.1 and 8.2 of the control, this ensures that the flip-flops 4.1 are set to one and thus the source operands are received in each cycle in the registers 10.1 - 10.N. A high level is applied to the first control input of switches 7.1–7.4, and a low level to the second control input; this ensures a constant input to input 22.1 of the coefficient h (i). The first output filter count is obtained after N / 2 clock cycles; at each subsequent clock cycle, a new count appears at the filter output.

Claims (1)

Claims An apparatus for calculating a convolution comprising two groups of N / 2 multipliers, N / 2 adders of the first group, N / 2 adders of the second group, N / 2 sum registers, N / 2 input data registers, where the input of the first input data register is The information input of the device, the input of the 1st 2i 2, ..., N / 2 input data register is connected to the output (1-1) of the input data register, output j-roQi 1, ..., N / 2 J the multiplier of the first group is connected to the first input of the j-ro adder of the first group, the output of the j-ro multiplier of the second group is connected by the second input of the j-ro adder of the first group, the output of which is connected to the first the input of the j-ro adder of the second group, the output of which is connected to the information input of the j-ro register of the sum, the output of the i-ro register of the amount register is connected to the second input (1-1) of the second adder of the second group the second input of the N / 2-nd adder of the second group is connected to the zero potential bus, This is because, in order to extend the functionality by calculating autocorrelation, N / 2 inverters, a group of N / 2 triggers, N / 2 And elements, N operand registers, N / 2 mode triggers, two groups of registers are introduced into it. , N four-input multiplexers, two two-input multiplexers and a synchronizer, the first and second time parameter inputs of which are device mode setting inputs, the first synchronizer output is connected to input data registers and registers of the first and second groups, with input With the inverter and synchronous inputs of the group triggers, the information input of the first operand register and the first information inputs of the first and second two-input multiplexers are connected to the information input of the device, the output (i-1) -ro of the input data register is connected to the information inputs (21-2) of the and (21-1) th register of operands, the output of the 1st register of input data is connected to the information input of the N-ro register of operands, the first input of the j-ro multiplier of the first group is connected to the output of the (2j-1) -ro register of the operand, the first j-ro input multiplier sec the second group is connected to the output of the 2j-ro register of the operand, the second input of the j-ro multiplier of the first group is connected to the output of the (2j-1) th four-input multiplexer, the second input of the j-ro multiplier of the second group is connected to the output of the 2j-ro four-input multiplexer , the output of the j-ro element And is connected to the synchronous inputs (2j-1) -ro and 2j-ro registers of the operand, the first input of the j-ro element And is connected to the direct high five 0 five 0 five 0 five 0 five by the j-ro trigger of the group, and the second input is by the j-ro output of the inverter and the jx synchronous input triggers of the mode and the sum register, the direct output of the i-th trigger of the group is connected to the information input of the (1-1) -th trigger of the group, direct The N / 2 trigger of the dead body is connected to the second output of the synchronizer, the forward output of the first mode trigger is connected to the first control inputs of the first and second four-input multiplexers, the forward output of the 1st mode trigger is connected to the first control inputs ( 21- -1) and 2i-ro four-input multiplexers and infor by the modulation input (1-1) of the mode trigger, the information input of the N / 2 mode trigger is connected to the third synchronizer output, the fourth output of which is connected to the second control inputs of the four-input multiplexers, the first and second information inputs of which are respectively the job inputs the coefficients of the first and second pulse characteristics of the device, the output of the first two-input multiplexer is connected to the third information input of the first four-input multiplexer and information input first first register of the first group, the output (1-1) of the first register of the first group is connected to the third information inputs (21-2) and (21-1) of the four-input multiplexers and information input of the 1st register of the first group, output ( 1 + N / 2-1) -th register of the first group is connected to the information input (1 + N / 2) -ro register of the first group, the output of the N-ro register of the first group is connected to the second information input of the first two-input multiplexer, the output of the second two-input multiplexer connected to the fourth information input of the first four-input mule l-typelexer and information input of the first register of the second group, the output (1-1) -th register of the second group is connected to the fourth information inputs (21-2) -th and (21-1) -th four-input multiplexers and information input of the 1st the second group register, the output (1 + N / 2 - 1) of the second group is connected to the information input (1 + N / 2) -ro of the second group register, the output of the N-ro register of the second group is connected to the second information input the second two-input multiplexer, the control inputs of the first and second two-input multiplexers are connected respectively to the fifth and sixth outputs of the synchronizer. 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