RU1830527C - Computer clock device - Google Patents

Abstract

The invention relates to devices for generating and / or distributing clock pulses and can be used in the construction of computer systems based on several digital computers of the same type. The purpose of the invention is to increase the accuracy of synchronization. The device contains rear

Description

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generator 1, counter 2, decoder 3. triggers 4, 5, elements 6-9, elements NOT 10-13, element OR 14, element EXCLUSIVE OR 15, element NAND 16, input 17 of the exact time signal of the general reference system , input 18 signal mode without

The invention relates to devices for generating and (or) distributing clock pulses and can be used in the construction of computer systems based on several of the same type of digital computers.

An object of the invention is to increase the accuracy of synchronization.

FIG. 1 is a diagram of a device for synchronizing a computing system; FIG. 2 - connection of devices priority selection schemes in a computing system.

The device contains a master oscillator 1, counter 2, decoder 3, triggers 4, 5, elements 6, 7, 8, 9, elements NOT 10, 11. 12, 1.3, element OR 14, element EXCLUSIVE OR 15, element NAND 16, input 17 of the exact time signal of the common reference system, input 18 of the signal of the operating mode without a common reference system, input 19 of the device priority, the general highway 20 of the computer system, the outputs 21 of the device.

Each channel of the device contains a priority selection circuit (Fig. 2) containing a trigger 5, an AND element 9, an EXCLUSIVE OR 15. element. Priority selection circuits for all channels are connected in series via the priority bus 19. The priority bus 19 of the first channel (device) is connected to a signal of a logical unit., I.e. the first device of the computing system has the highest priority.

The device synchronizes each digital computer of the computing system with accurate time signals arriving at input 17 smoothly with a one-step discrete frequency of the operating frequency of the master oscillator 1.

The device operates as follows.

In the initial state, the triggers 4, 5 are in the single state, i.e. at the inverted output of trigger 4, there is a zero potential, and at the direct output of trigger 5, there is a single potential.

The master oscillator 1 generates a continuous series of clock pulses, which is fed to the counting input of the counter 2.

general reference system, priority input 19, device outputs 21. In the absence of accurate time signals, the channels of the digital computer of the computing system are synchronized with each other through the device having the highest priority. 2 ill.

According to the state of counter 2, at the outputs of the decoder 3, in synchronous operation of the device with an accurate time signal, m output signals are generated, and in non-synchronous operation mode, (t-1) output signals are generated. The non-synchronous operation of the device according to the exact time signal arriving at input 17 is fixed on trigger 4. Depending on the state of trigger 4, the last n-th signal at the output of the IL element 14 is generated by the counter 2 receiving the state m or (t-1 ) When the last (n-1) signal appears at the output of the OR element 14, the counter 2 is zeroed and the unit is written to trigger 4, i.e. transition to the next cycle of generating control signals.

In synchronous operation of the device with an accurate time signal, the control signal generation cycle is constant, i.e. the last control signal of the cycle is generated at the mth value of counter 2.

During non-synchronous operation of the device with an accurate time signal, the cycle of generating control signals decreases by the value of the duration of one cycle (At) of the frequency of operation of the master oscillator 1. In this case, the number of control signals in the cycle remains unchanged, i.e. the last control signal of the cycle is generated at the (t-1) -th value of counter 2,

In the absence of accurate time signals on the bus 17 (in case of a malfunction or the absence of a common reference system), a signal of the operating mode without a common reference system is supplied to all devices via bus 18. At the same time, on the device element 17, the signal from the m-th input of the decoder 3 to the device outputs 2.1 is prohibited and the AND-NOT element 16 opens the output of the priority circuit to the common highway 20. When a signal is generated at the output of the (t-2-) decoder 3, the output (p-1) of the device through the element HE 12 is zeroed trigger 5. In this case, the output of the element And 9 of the first device of the computing system sets the zero potential, which blocks the priority selection schemes of all

other devices (Fig. 2). The generated zero potential at the output of the AND-NOT element 16 of the first device through the common highway 20 in each device enters through the element NOT 13 and the OR element 14 to the outputs 21 of the device. In this case, counter 2 is reset and one is written to triggers 4, 5, i.e. transition to the next cycle of generating control signals. Together, trigger 5 and the element NAND 16 control the health of the device, i.e. sequential formation of counter values 2 (t-2), etc.

When the first device is excluded from operation, the second device has the highest priority for synchronization, etc.

Claims (1)

SUMMARY OF THE INVENTION A device for synchronizing a computing system comprising a master oscillator, a counter, a decoder, two AND elements, an OR element, a NOT element, a trigger, the inverse output of the master oscillator being connected to the counting input of the counter, the group of outputs of which are connected respectively to the group of inputs of the decoder , (t-1) -th output of which is connected to the first inputs of the first and second elements And, the input of the exact time signal of the overall frame of reference of the device is connected to the second input of the second element And and through the first element NOT - with the R-input of the first trigger, the inverse output of which is connected to the second input of the first element And, the zero potential bus of the device is connected to the K-input of the first trigger, the outputs of the decoder from the first to (t-2) -th are respectively outputs with the first in the (n-1) th device, the outputs of the first and second elements AND are connected respectively to the first and second inputs of the element OR, the output of which is connected to the installation input in the counter O, with the J- and C-inputs of the first trigger and is the nth output of the device, characterized in that. in order to increase the accuracy of synchronization, a trigger, two AND elements, an NAND element, three NOT elements, an EXCLUSIVE OR element are introduced into the device, the mth output of the decoder being connected to the first inputs of the third AND element and the NAND element, mode signal input operation without a common reference frame of the device is connected to the second input of the AND element and through the second element NOT to the second input of the third AND element, the (t-2) -th decoder output is connected via the third element NOT to the R input of the second trigger, direct the output of which is connected to the first input of the fourth of the AND element, the input of the device for connecting to the common trunk of the synchronized computing system through the fourth element is NOT connected to the third input of the OR element and to the J- and C-inputs of the second trigger, the output of the third AND element is connected to the fourth input of the OR element. the zero potential bus of the device is connected to the K-input of the second trigger, the output of the fourth AND element is an extension of the device for connecting to the priority input of the subsequent device and to the first input of the EXCLUSIVE OR element, the priority input is connected to the second inputs of the fourth AND element and the EXCLUSIVE OR element, the output of which is connected to the third input of the AND-NOT element, the open collector output of which is connected to the output of the device for connecting to the general line of the synchronized computing system For example, the priority input of the first device is connected to the unit potential bus of the device.