SU1748241A1 - Digital pulse-width modulator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in measuring and converting communication and control systems. The purpose of the invention is to improve the noise immunity. Digital pulse-width modulator contains generator of 1 rectangular pulses, counters 2, 3 pulses, trigger 4 characters, counting trigger 5, triggers 6, 7, elements OR 10, 11, 12, inverter 16, elements 17, 18, 19, 20 matches, pulse formers 23, 24, limiting unit 31, reset unit 32, switches 33, 34, output buses 37, 38, input buses 41. Introduction, to the trigger modulator 8.9, the elements OR 13, 14, 15, the elements 21, 2 coincidence, the formers 25, 26. 27, 28, 29, 30 pulses, the switches 35, 36 and the output buses 39, 40, made it possible to increase the device immunity due to the restoration of the correct operation of the modulator in case of interference from interference in the next clock interval. 3 il.

Description

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Claims (1)

Claim A digital pulse-width modulator containing the first and second pulse counters, a sign trigger, a counting trigger, four coincidence elements, two triggers, an inverter, three OR elements, two switches, two pulse shapers, a restriction block, a reset block and a rectangular pulse generator, an output which is connected to the first inputs of the first and second OR elements, the second inputs of which are connected respectively to the direct and inverse outputs of the sign trigger, the direct output of which is connected to the control inputs of the first and second utensils, the first input is with the sign bus and the sign input of the restriction unit, and the second input is with the output of the inverter, the input of which is connected to the information recording inputs of the first and second pulse counters, the bit inputs of which are connected respectively to the outputs of the restriction unit and the common bus, transfer outputs the first pulse counter is connected to the inputs of the first coincidence element, the output of which is connected to the first input of the third OR element, the output of which is connected to the input of the first pulse shaper, and the second input with direct output a counting trigger house, the reset input of which is connected to the output of the reset unit and the first 5 input of the second, third and fourth coincidence elements, the second input of the second of which is connected to the transfer output of the second pulse counter, and the output to the inverter input, while the bit inputs the 10 ke restrictions are connected to the input signal buses, the first inputs of the first and second switches are connected respectively by the inverse and direct outputs of the first and second triggers, and the outputs of the first 15 and second switches with the first and second output w inami, characterized in that, in order to increase noise immunity, the third and fourth triggers, the fifth and sixth elements of coincidence, the fourth, fifth and sixth elements of OR, the third, fourth, fifth, sixth, seventh and eighth pulse shapers are additionally introduced into it, the third and fourth switches, the outputs of which are connected to the 25th third and fourth output buses, the control inputs are with the direct output of the sign trigger, the first input of the third switch is with the first input of the first switch, the second input of the third switch is from the second the input of the first switch and the inverse input of the third trigger, the first input of the fourth switch with the second input of the second switch and the direct output of the fourth trigger, 35 and the second input of the fourth switch with the first input of the second switch, the reset inputs of the first, second, third and fourth triggers are connected respectively, with the outputs of the third, fourth, fifth and sixth coincidence elements, the first inputs of which are connected to the output of the reset unit, the second inputs of the third and fifth coincidence elements, respectively with the outputs of the fourth and eighth pulse generators, and the second inputs of the fourth and sixth coincidence elements, respectively, with the outputs of the fourth and sixth elements OR, the first inputs of which are connected to the overflow output 50 of the second pulse counter and the counting input of the counting trigger, and the second inputs, respectively, with direct and the inverse outputs of the counting trigger, the inverse output of which is connected to the first input of the fifth. 55 OR element, the second input of which is connected to the output of the first coincidence element, while the output of the first and second OR elements is connected respectively to the inputs of the reverse and direct counting of the first pulse counter, the output of the rectangular pulse generator is connected to the counting input of the second pulse counter, the output of the third element OR connected to the installation input of the trigger and through the first and second pulse shapers connected in series with the installation input of the second trigger, the output of the fourth element OR through the third pulse shaper with the input of the fourth pulse shaper, the output of the fifth OR element is connected to the installation input of the third trigger and through the fifth and sixth pulse shapers connected in series with the installation input of the fourth trigger, and the output of the sixth OR element is connected through the seventh pulse shaper with the input of the eighth shaper pulses. 4J 44 a ~ 1 counter2 || 7 ”G b Trigger \ Shaper 24 || g | Trigger b ^ counter 3 C || e ον. trigger | well I) Shaper26] | 3 Trigger I I and If Shaper 28 | TO Trigger 9 l Shaper JO | m tire 57 ♦ n shi at 33 Λ ABOUT bus J 9 ~ * P tire 40  ....... —--------------------- ................... - ------------------> ψ _υί .3