SU1659710A1 - Digital data recorder - Google Patents

Abstract

The invention can be used to graphically register digital information. The purpose of the invention is to reduce the error in registering digital information. The goal is achieved by using the maximum possible number of gradations of the luminance of the information recording medium with a consistent number of gradations of the luminance of the information recording medium and the minimum number of the digital code of the input information by correcting the nonlinearity of the dependence of the optical density of the information recording medium on the recording pulse duration. Into a device containing a writing element 1, a key 2 and a frequency divider 6, a decoder 4, a shift register 7, three triggers 8–10, inverters 11, 12, and 1 are entered. W Ј

Description

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The invention relates to the registration of information, namely, devices for registering digital information.

The aim of the invention is to reduce the error in registering digital information.

The drawing shows a block diagram of the proposed device for registering digital information.

The device for registering digital information contains a serially connected writing element 1 and a key 2, an input bus 3 of information connected to the inputs of the decoder 4, an input bus 5 of synchronization connected to the input of a frequency divider 6. In addition, a device for registering digital information contains a shift register 7 connected by information inputs to outputs of decoder 4, a synchronization input to synchronization input bus 5, first, second and third triggers 8-10, first 11 and second 12 inverters. The sync input bus 5 is connected via the first inverter 11 to the first input of the third flip-flop 10 connected by the second input to the output of the second flip-flop 9 and to the control input of the shift register 7. The shift register 7 is connected by the installation input through the second inverter 12 to the first input of the second trigger 8, to the input of the key 2 and to the output of the first trigger 8 connected by the first input to the output of the shift register 7. The first trigger 8 is connected by a second input to the output of the frequency divider 6 and the third input to the auxiliary output of the decoder 4. The second trigger 9 is connected by a second input to the output of the third trigger 10.

The device for registering digital information works as follows.

At the input of the decoder 4 receives a three-digit digital code to be registered. The decoder 4 converts it into the corresponding decimal code, and the signal from one of the outputs of the decoder 4 is fed to the information input of the shift register 7.

The frequency divider 6, to the input of which the reference frequency signal arrives, generates a clock signal with the information reading frequency, the positive differential of which triggers the first trigger 8. The shift register 7 is switched to the parallel recording mode of the input information, the information from the outputs of the decoder 4 is copied to it. After recording the information, the shift register 7 is switched to the pulse shift mode. For each pulse of the reference frequency arriving at

the synchronization input of the shift register 7, the information is shifted one cell to the right until the signal appears at the output of the shift register 7. The first trip 8 returns to the initial state, the signal from its output sets to the initial state the shift register 7. At the same time, at the input of the first trigger 8, an recording pulse is generated with a duration that corresponds to the digital code of the input information. Formed at the output of the first trigger 8, the pulse opens the key 2 for a time equal to the duration of the recording pulse. Each of the values of the digital input code corresponds to a certain gradation of brightness (optical density) of the recording medium, and for each of the gradations of brightness (optical density} of the recording medium, the curve of the optical density of the recording medium versus the recording pulse duration is determined at a constant recording current the duration of the recording pulse, i.e. the gradation of brightness, corresponds to the duration of the pulses. The duration of the recording pulse is chosen to be multiple of the period Ore frequency. The minimum duration of the recording pulse is selected by the corresponding optical

0 the density of the first gradation of the luminance of the recording medium.

In the frequency divider b, the reference frequency is divided by the required number of times, and pulses are formed at the output of the frequency divider 6.

5 On the leading edge of the clock pulse from the output of the frequency divider 6, the first trigger 8 triggers. On the leading edge of the pulse from the output of the first trigger 8, the second trigger 9 switches,

0 a signal from the output of which flips to the third trigger 10. The reverse transfer of the trigger 10 is performed by the leading edge of the reference frequency pulse received from terminal 5 through the inverter 11. The signal from the output of the 5 and the trigger 10 sets the trigger 9 to its initial state, and at the output of the trigger 9 a pulse is formed, which is fed to the input of the P / S register 7 and switches the register 7 to the parallel recording mode of the input information, on the leading edge of the first reference frequency pulse (pulse O) received during the action of the signal generated by igger 9, there is a census of information from the inputs Ot fj On into register cells 7, and

one of the outputs of the decoder 4, if the input code is 0, is written into the register cell 7 T, and the remaining inputs of the register, 7 are written O. If the code is input

information is 0. then from the output of the decoder 4 on which the zero code value of the input information is deciphered, the input of the installation of the trigger 8 receives a signal that blocks the trigger 8, and the trigger 8 stops responding to the signals arriving at its information inputs. With the end at the P / S input of the pulse register 7 from the output of the trigger 9, the register 7 switches the level O to the pulse shift mode. On the leading edge of the reference frequency pulses (pulses 1, 2, etc.), information in register 7 shifts until a signal appears at the output of register 7. The signal from the output n of register 7 goes to the second input of trigger 8 and returns it to its original state the The rising edge of the pulse from the output of the trigger 8 is made (via the inverter 12U. Setting the register 7 to the input R to the initial state.

Claims (1)

DETAILED DESCRIPTION OF THE INVENTION A device for registering digital information containing a serially connected writing element and key, 0 five 0 five an information input bus, a sync input bus connected to the input of a frequency divider, characterized in that. In order to reduce the error in registering digital information, a descrambler connected via an input to the input information bus, a shift register, three triggers, two inverters are entered in series with it, the shift register is connected by a synchronization input to the input synchronization bus and through the first inverter to the first the input of the third trigger, the installation input through the second inverter to the interconnected key input, the first input of the second trigger and the output of the first trigger, the control input to you the second trigger and the second input of the third trigger and the output to the first input of the first trigger connected by the second input to the output of the frequency divider and the third input to the auxiliary output of the decoder, and the third trigger is connected to the output of the second input of the second trigger.