SU1027828A1 - Device for generating counter check bit - Google Patents

Abstract

A DEVICE FOR THE FORMATION OF THE CONTROL DISCHARGER OF THE COUNTER, containing a counter trigger, a counter and epeiteitis NAND according to the number of discharges of the counter, the output of each element NANDE, starting from the first, is connected with 2-3 2--2 - / first input of the next element AND -NOT | the second inputs of the elements AND-NOT, starting from the first, are connected respectively to the output. The bits of the counter start from the oldest, the output of the last element AND – NOT connects. with a counting input of the control trigger, a synchronization input, which is connected to the input signal, characterized in that, in order to expand the scope of application by using it in the counter both odd and even. the number of bits, it introduced an additional element AND-NOT, the inputs of which are connected to the outputs of the bits of the counter, the output of the additional element AND-NOT connected to the third input of the last element AND-NOT. 2-f

Description

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The invention relates to a hydraulic cleaning technique and can be used for implementing technical means in this field.

The known device for the formation of a check digit counter 5, containing (1-bit binary counter, L + 2 elements of inequality and constant trigger | Jll.

Unreleased for this device is its relative complexity.

It is known that the device for forming the check digit of the counter, containing the counter-trigger, the counter, and the II – I elements according to the number of counts of the counter, 15 counts, the output of each NAND element, starting with the first element NAND, the second inputs of elements NAND, starting from the first, connected respectively to the outputs of rows of the counter, starting from the senior

In the known device, the value of the check bit, which is the addition of the number of units of a number that is in the counter to odd (even), is formed not on the basis of the summation over Y "O (E2 ZO on the elements AND-NOT sums of the counter contents of the counter in this and subsequent cycles The logical level formed at the same time on the counting input controls the operation of the control trigger, which will give 5 to the gauge of the next cycle of the next clock .23.

A disadvantage of the known device is the incorrect formation of the value of the check bit in the case of re-Q or counting with an odd number of bits, which limits the scope.

Purpose: the invention - the expansion area. in the counter by using both an even and an odd number of bits.

This goal is achieved by the fact that in the device for the formation of the control - - ,. the first digit of the counter, containing the control trigger, the counter and the elements AND-NOT 50 by the number of bits of the counter, the output of the 1st element, Starting from the first, is connected to the first input of the subsequent AND-AND element, the second inputs of the AND-elements, starting from the first one, 55 are connected respectively to the outputs of the counter bits, starting from the senior one, the output of the last element is NOT the one connected to

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the input of the control trigger, whose sync input is connected to the input terminal, an additional NAND element is introduced, whose inputs are connected to the counter bits, the output of the additional NAND element is connected to the third input of the last NAND element.

The drawing shows a diagram of the device and the formation of a test bit of a five-bit counter.

The device contains the counter 1, the elements AND-NOT,,, AND, the elements AND-NOT 3 and 4, the control trigger 5 and the input-bus 6.

The outputs of the bits of the counter 1 from the first to the fifth are connected by g inputs of the element AND-NO 4 and respectively with the first inputs of the elements AND-HE 3,,, and whose outputs are connected respectively with the counting input trkgge, pa 5, with the second input of the element AND -NOT. 3 and with the second inputs of the elements AND-NOT 4, and. the output of the element AND-NOT 4 is connected to the third input of the element AND-NOT 3. The device operates as follows. When a counting pulse arrives at the input of counter 1, the NAND elements and the NAND element 3 at the counting input of trigger 5 form a logical level corresponding to the sum of the sum of content units of the counter in this and subsequent cycles. At the output of the trigger 5 at this moment, the signal level corresponds to the value of the counter-compression bit in the given cycle. When a pulse arrives at the synchronization input of trigger 5, a check bit value of the next clock cycle is formed at its output. When the output of the counter bits of the unit levels at the output of the element IS-NOT 3, there is a zero level, which allows you to change the value of the check bit in the next cycle, because in a slash state of the counter bits (at the outputs of the bits counter zero levels) at the output of the element AND-NOT 3 is present. zero level.

 Thus, with a minimum of 1 B, the result of the addition of one EID-4 epi- element, analyzing the appearance at all direct outputs of the 1 unit counter, it became possible to correctly formulate the check bit at the next drift of the counter impulse when the counter overflow occurs. Incorrect formation of counter-discharge & bit in the event of the addition of counters with an odd number of bits for transmitting information

31О27828- 4

on lines of communication requires in devices. The invention eliminates irregularities.

receiving information from the application of schemes, the formation of a check bit in the next for n (W (1 "cycle) in accordance with the overflow of the counter with an odd

with it a corrective control circuit with a number of bits and thus apply a chetiness .to even parity. This leads to sa-snimb to counters with any number

the difficulty of creating simple tools and provides the government with a form of control, especially for computing the control bit at work

a system with a complex branched structure. the counter in the cycle.

Claims (1)

A DEVICE FOR FORMING A CONTROL DISCHARGE OF A COUNTER containing a control trigger, a counter and AND-NOT elements by the number of the first input of the subsequent AND-NOT element, the second inputs of the AND-NOT elements, starting from the first, are connected respectively to the outputs of the counter bits, starting from the old -. Moreover, the output of the last AND-NOT element is connected to the counting input of the control trigger, a synchronization input which is connected to the input bus, characterized in that, with the extension circuit of the field of application due to its use in the counter with both even and odd . by the number of bits, an additional AND-NOT element has been introduced into it, the inputs of which are connected to the outputs of the bits of the counter, the output of the additional ele- szszm ^pp 7) § 1027