SU924867A1 - Modulo 6 scaling device - Google Patents

Description

I

The invention relates to automation and computer technology and can be used in various devices for dividing the pulse frequency by a factor of six.

Known scaling device modulo six, performed on the triggers with separate inputs and elements of AND-NOT P.

A disadvantage of the known device is a large number of logical elements, which causes a low reliability of the device.

The closest in technical essence to the present invention is a modulo-six recalculation device containing a memory trigger and a switching trigger in the first discharge, two AND-NOT elements in the second discharge and a memory trigger, the T-trigger executed in the third discharge on two switching triggers and one memory trigger, the single output of the first memory trigger is connected to the input of the first AND-second element of the second discharge and to the single input of the first switching trigger whose zero output is connected to the memory trigger input of the given bit and with the other input of the first element NAND of the second bit, the zero output of the memory trigger of the second bit is connected to the input of the second element NAND of the given

10 bits and with zero inputs of the memory trigger and the switching trigger of the first discharge, the output of the first AND – NE element of the second discharge is connected to the single inputs of the memory trigger blocks

15 of the first and second bits, and the outputs of the first and second IS-NOT elements of the second bit are connected respectively to the zero inputs of the first switching trigger and to the single

The inputs of the third switching trigger of the third bit, the single output of the third bit memory trigger are connected to the single input of the first switching trigger of this bit, the zero output of which is connected to the single input of the fM memory of this bit, and the single output with zero input the second switching trigger of the given bit Ya, the unit output of which is connected to the zero inputs of the trigger and the first switching trigger of the third bit, the zero output of the first switching trigger The single output of the third switching trigger of the third discharge is connected respectively to the zero inputs of the switching trigger of the first discharge, to zero inputs of the second memory trigger and to the inputs of the second AND-NOT element of the second discharge, and to the zero input of the switching trigger of the first bit, to the input of the first element IS-NOT of the second bit, to the zero input of the first switching trigger and to the single input of the second switching trigger of the third bit, the input is connected. A disadvantage of the known device is that it has a large number of inputs in the elements used and a large number of connections between the elements, which significantly reduces the reliability of its operation. The purpose of the invention is to increase the reliability of the device. The goal is achieved by the fact that in the scaling device of the PB module six, containing in the first position a memory trigger and a switching trigger, in the second section an AND-NES element and a memory trigger, in the third discharge a memory trigger, and a single output the first memory trigger of the first bit is connected to the first input of the second-level NAND element and to the single input of the switching trigger of the given bit, the zero output of which is connected to the first single input of the first-memory memory trigger and to the second input of the second AND-N element razr yes, the output of which is connected to the second one; the first memory trigger input of the first bit and the single memory trigger input of the second bit; the zero memory trigger output of the second bit is connected to the first, left-hand memory trigger inputs and the mutational trigger the first bit, the second bus is connected to the second zero input of the switching trigger of the first bit and the input bus is connected to the third input of the NAND element, entered the second bit of the switching trigger, and the third bit has the NAND element and an additional trigger, zero which input is connected to the output of the IS-NE element of the second bit, and the single input is with the zero output of the memory trigger of the third bit, the single output of the switching trigger of the second bit is connected with the third zero input of the switching trigger of the first bit and with zero inputs of the trigger the memory of the second and third bits, the zero output of the memory trigger of the second bit is connected to the zero input of the switching trigger of the given bit, with the single inputs of which are connected respectively the input bus and the output element This IS-NOT is the second bit, the output of the IS-TH element of the third bit is connected to the single input of the memory trigger of this bit, and the input of the IS-IS of the third bit is connected respectively to the output of the IS-IS element of the second bit, zero output of the trigger memory of the second bit and zero 1 output of the additional trigger of the third bit. . The drawing shows a diagram of the scaling device modulo six. The device contains switching triggers on the elements li AND-NOT, an additional trigger on the elements AND-NOT 5-6, memory triggers on the elements AND-NOT 7-12, elements 13 and 13 of the second discharge, element II. And the third discharge and the input bus 15The device works as follows. In the initial state, the input signal on bus 15 is absent (equal to the logical o). In this case, at the outputs of the elements 1,2,3,5,8,10,12,13 and k, the signals are equal to logical 1, and at the remaining outputs of the elements AND NONE - logical 0. With the arrival of the first input pulse at the output of the element I - NOT 2 a logical O appears, which sets the first-bit memory trigger on the AND-HE elements 7-8 to one state and blocks the IS-NOT element 13 from possible triggering in a given clock cycle. In the pause after the first pulse at the output of the element AND NOT 2

logical 1 appears, and the output of element 1 is logical o,

With the arrival of the second input pulse, the logical Q appears at the output of the NAND 13 element, which sets the second bit memory trigger on the NAND elements to an additional one state. the trigger on the AND-NE elements 5-6 to the zero state and blocks the AND-NOT elements 3.7 and W from the possible switching in the second cycle.

In the pause after the second pulse, a logical O appears at the output of the NAND 7 element, which will block the NAND 13 element.

The third input pulse causes the appearance of a logical O at the output of the AND-NO 3 element, which sets the second-bit memory trigger to the zero state and blocks the AND-NE element 2 and 12. The appearance of the logical 1 at the output of the AND-NE element causes the appearance of a logical 6 at the output of the element NAND, and therefore a logical 1 at the output of the element NAND 11.

In the pause after the third pulse, the logical 1 appears at the output of the AND-HE 3 element, and the logical 0 at the output of the IS-NOT 12 element.

Further, the cycle of operation of the first two bits is repeated. With the arrival of the sixth pulse, logical O from the output of the AND-HE element 3 sets the third-bit memory trigger to the zero state.

Thus, the device reduces the number of inputs in the elements used and the number of connections by the elements, which leads to a simplification of the device and an increase in the reliability of its operation.

Claims (2)

1. Gutnikov B.C. Integrated electronics in measuring devices. L., Energie, 197, p. 85, .ris. . 2. USSR author's certificate f, cl. H 03 K 23/02, 1976 (prototype).