SU1503065A1 - Single pulse shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices. The purpose of the invention is to expand the range of variation of the control pulse duration. A single pulse shaper contains RS - trigger 1, element AND-NOT 2, element NO 3, element AND 4, element AND-OR 5, counter 6, decoder 7. Introduction to the RS scheme - trigger 8, element AND-HE 9, elements NOT 10.11 ensures the operation of a single pulse generator in a wide range of variation of the duration of the control pulse. This is achieved due to the fact that the dependence of the duration of the output pulse on the duration of the input pulse is excluded. As a result, it is possible to use the same circuit for working with a generator issuing a control pulse of different duration and, consequently, an increase in the unification factor of the generator. 2 Il.

Description

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The invention relates to a pulse technique and can be used in the lI front computing technology.

The purpose of the invention is to expand the range of variation of the control pulse duration.

FIG. 1 shows a diagram of a single pulse generator J in FIG. 2 — a diagram of the operation of a single pulse generator for two cases: when the duration of the input control signal is longer than the expected duration of the output pulse and when it is shorter.

A single pulse shaper contains an RS-flip-flop 1, the first element is NAND 2, the first element is NOT 3, the element is AND 4, the element is H-NI1 5, the counter is 6, a decoder 7, the second is RS-flip-flop 8, the second element is NAND 9, the second 10 and third 11 elements are NOT, while the inputs of the second element NAND 9 are the inputs of the device, and the output is connected to the single input of the second RS flip-flop 8, the zero output of which is connected to the output of the second element NOT

10, the input of which is connected to the zero output of the first RS flip-flop 1, the zero input of the second RS flip-flop B is connected to the input of the third element NOT

11, the output of which is connected to the first input of the AND 4 element and the zero input of the counter.

FIG. 2 are labeled in. 1 and in. 2 control input and clock input, respectively, o. 11 - the output of the element NOT 11. The designations of the outputs of the elements in the diagram correspond to the numbers of the elements in the circuit (figure 1).

A single pulse shaper works as follows.

In the initial state at the control input there is a low logic level, RS-flip-flops 1 and 8 are set to 1 and zero, respectively. In this case, the output of the imager is a low logic level. When a high level of the control signal appears at the input of the NES-9 element, the leading edge of the next clock pulse RS flip-flop B is transferred to the one state, while its zero output contains the logical zero signal, and is the signal of a logical unit. At the same time

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the counter is rotated and the AND 4 element is opened, skipping cycles to the counting input of counter 6. The counter state is de-encrypted by the decoder 7, at one of the outputs of which there is always a logical unit. When a logical unit from the output of the decoder 7 coincides with a logical unit, a logical unit appears at one of the control buses in the same AND group, and at the output of the AND-5 element, which, together with the logical unit from the HE element 11, allows the RS-trigger 1 to be reset negative a signal from the NAND 2 element. At the zero output of the RS flip-flop 1, there is a logical unit at the moment corresponding to the clock pulses. At the output of the element HE 10, a low / level signal appears, bringing the RS flip-flop 8 to the initial state. At the output of the element NOT 11, a logical zero level is set, which locks the AND-HE 2 and And 4 elements and resets the counter. At the moment of switching, the zero shoulder of the RS-flip-flop 1 operates as an IS-NOT element, therefore upon termination of the logical zero signal from the IS-NOT 2 element the RS-flip-flop 1 state depends on the input control signal. With a single logical level of the input signal at the output of the zero shoulder of the RS flip-flop 1, there is a logical one, with a zero logical level of the input signal - a logical zero.

The invention provides for the formation of a single pulse in a wide range of variation of the duration of the control pulse due to the fact that the dependence of the duration of the output pulse on the duration of the input pulse is excluded. As a result, it is possible to use the same scheme for working with devices that produce a control pulse of different duration, and, consequently, the coefficient of unification of the device is increased.

Claims (1)

Invention Formula A single pulse shaper containing an RS flip-flop, the zero input of which is connected to the output of the first NAND element, the first input of which is connected to the output of the first the element is NOT, the second input is with the first input of the AND element, and the third input is with the output of the I-LLL element, the input of the first element is NOT connected to the second input of the AND element and connected to the input of the clock of the pulse generator, the output of the AND element is connected to the counter input of the counter, outputs which are connected respectively to the inputs of the decoder, the outputs of which are connected to the first inputs of groups AND of the AND-OR element, the second inputs of groups AND of which are connected to the control buses, the single input of the RS flip-flop is connected to the control input of the driver, different by that. in order to extend the range of variation of the control pulse duration, a second RS flip-flop is entered into it, the second IS-NOT element, the second and third NO elements, while the inputs of the second AND-NO element are the driver inputs and the output is connected to the single input the second RS flip-flop, the zero input of which is connected to the output of the second element NOT, the input ko-. This is connected to the zero output of the first RS-flip-flop, the zero output of the second RS-flip-flop is connected to the input of the third element NOT, the output of which is connected to the first input of the element I, and to the input of the counter.