SU1443171A1 - Divider of pulse recurrence rate - Google Patents

Description

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The invention relates to a pulse technique and can be used in devices for automation and telemechanics.

The aim of the invention is to expand the functionality of the frequency divider by allowing the initial code of the L number to be set at a device divi- sion ratio of the form ii, where 1 L iK, i is the number of input pulses, while increasing the reliability of the installation by generating installation pulses guaranteed duration.

The drawing shows an electrically functional diagram of a pulse frequency divider.

The pulse frequency divider contains the first and second counters 1 and 2 pulses, the first and second inverters 3 and 4, element 5, the first and second triggers 6 and 7, element W-NOT 8, input bus 10, control bus 11 and bus 12 initial installation, while the information inputs of the second counter 2 pulses are connected to the corresponding outputs of the bits of the pulse counter 1, the summing input of the first counter of 1 pulses is connected to the first input of the And 5 element, the output of the STI-NE element 8 and the second recording enable input the second counter 2 pulses . the subtractive input of which is connected to the output of the element 5, the transfer output of the counter of 2 pulses is connected to the input of the first inverter 3, the output of which is connected to the clock input of the first trigger 6, the inverse output of trigger 6 is connected to the clock input of the second trigger 7, the forward output of which connected to the second input of the element OR NOT 8, and the reset input to the second input of the element 5 and the output of the second inverter 4, respectively, the reset input of the first trigger 6 is connected to the input of the second inverter 4 and to the input bus 9, the information inputs of the first account Chika I connected to the bus

11 control, write enable input of the first counter 1 connected to the bus

12 of the initial setup, the direct output of the first trigger 6 is connected to the first input of the SH-NE 8 element and the output bus 10.

The pulse frequency divider operates as follows.

On bus 11, a LO number code is set. Low level applied to

bus 12, is fed to the write enable input of the counter 1 and pulses, and the code of the number L is recorded in counter 1.

Let the number L 1 be recorded in the pulse counter 1, i.e. code 00 ... 1 is present on the control bus II. At the same time, there are no pulses on bus 9, and at the output of element 8, the subtractive input of the counter 2 pulses and its transfer output, are high levels.

Bus 9 receives the first pulse. A negative edge appears at the positive edge of the first pulse at the output of inverter 4, and a low level is established at the subtracting input of the pulse counter 2. Since the contents of counter 2 pulses are zero, a negative edge appears at its transfer output, which triggers through inverter 3, ger 6. At the output of element 8, a low level is set, the counter of 2 pulses is lowered by this low level. ., and the contents of the pulse counter 1 are rewritten into the pulse counter 2.

At the end of the first pulse, the trigger 6 is reset, on the bus 10 the output pulse is completed in response to the first input, a positive front from the inverse output, the trigger 6 is triggered by the trigger 7, the output state of the element 8 does not change, the subtracting input of the counter 2 with pulses is present low level.

Tire 9 receives a second pulse. On the positive edge of the second pulse, trigger 7 is reset, the output of element 8 is set to a high level, and the counter 2 of pulses goes into the Counting state, the contents of pulse counter 1 are increased by one and the element 5 is opened.

On the negative front of the second pulse through the inverter 4 and the element 5 from the counter 2 pulses, one is subtracted, and its contents again become equal to zero.

Bus 9 receives the third pulse to which the frequency divider responds as well as the first pulse. Only now, from the pulse counter 1 to the pulse counter 2, the content is rewritten one more than in the previous cycle.

31443171

Thus, in response to 1.3, 6, with an output bus and with a direct output of 10, 15, etc. the pulses received by the first flip-flop, the inverse output of the pin 9, are formed on the bus 10 that is connected to the clock input second output pulses, i.e. a trigger is implemented, the direct code of which the division factor 21 i is connected to the second input of the element

OR NOT, the output of which is connected to

F O P M V l YAI CHOOSHVIA

   the summing input of the first counter

A pulse frequency pulse divider, a recording resolution input ow, containing the first pulse counter of which is connected to the initial bus, whose information inputs are set to the recording resolution input connected to the control bus, the outputs of the second pulse counter and to the first pulse counter. information inputs of the input element And, the output of which is soy, the second counter and pulses, the input is dinane with the subtractive input of the second and output bus, which distinguishes -15 pulse counter, the output of the transfer so that Oogo through the first inverter connectivity functionality, it is not connected with the clock input of the first trigger; the first and second inverters are entered, the pa whose input is connected to the input element And, the first and second triggers, bus and through the second inverter - with; The bus of the initial installation and the element 20 by the second input of the element I and to the input of the WL-NOT, the first input of which is connected to the reset of the second trigger.

Claims (1)

Claim Pulse repetition rate divider containing the first pulse counter, the information inputs of which are connected to the control bus, the outputs are bitwise with the information inputs of the second pulse counter, input and output buses, distinguishing -15 with the fact that, in order to expand the functionality , the first and second inverters, the And element, the first and second triggers, the initial installation bus and the IPI-NOT element, the first input of which is connected to the output bus and with the direct output of the first trigger, the inverse output of which connected to the clock input of the second trigger, the direct output of which is connected to the second input of the OR-HE element, the output of which is connected to the summing input of the first pulse counter, the recording enable input of which is connected to the initial setup bus, with the recording permission input of the second pulse counter and with the first input element And, whose output is soy, is dined with a subtracting input of the second pulse counter, the transfer output of which through the first inverter is connected to the clock input of the first trigger, the input of which is connected to the input bus and Res second inverter - s; the second input of the And element and with the reset input of the second trigger.