JPS6347083Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a frequency doubler generating circuit that generates pulses of twice the cycle from an input signal of a pulse train.

Conventionally, there has been a circuit of this type as shown in FIG. In Figure 1, the input signal of the pulse train
f _IN is an exclusive OR gate (hereinafter referred to as gate)
1 along with the Q output of flip-flop 2. The output of gate 1 is supplied to the T (clock) input of flip-flop 2 and led to the outside. The output of flip-flop 2 is its D
(data) supplied to the input. To simplify the explanation, let us assume that the input signal f _IN consists of a pulse train with a duty ratio of 50%. As is clear from the circuit configuration, the signal f _put output from gate 1 is
It consists of a pulse train generated at the rising and falling edges of the input signal _fIN , and has a half period, that is, twice the frequency.

Conventional frequency doubler generation circuits are configured as explained above, so even if a noise pulse is superimposed on an input signal, it generates a pulse at the rising and falling edges of the input signal without distinguishing it from the input signal. Therefore, it had the disadvantage that the reliability of the circuit was not high.

This idea was made in order to eliminate the drawbacks of the conventional circuit as mentioned above.The period during which the gate output is high is counted by a counter, and the count result is set to a preset value corresponding to the input signal. It is an object of the present invention to provide a frequency doubler generating circuit that can improve the reliability of a signal by inputting a pulse to a flip-flop only when the frequency reaches the maximum frequency.

An embodiment of this invention will be described below with reference to FIG. As shown, the input signal f _IN is input to gate 1 along with the Q output of flip-flop 2, and the output of flip-flop 2 is applied to its D input. The output of gate 1 is G of counter 3
(Gate) input. Counter 3 receives a clock signal f whose cycle is sufficiently higher than that of the input signal f _IN .
c is supplied to the IN (clock) input, and when the G input is activated, a counter is performed based on the clock signal f _c . Counter 3 also has an OUT (count) output that goes low when counting reaches a certain value, and an R (reset) input that resets itself with a low OUT output. counter 3
The OUT output of is supplied to the T input of flip-flop 2 and led to the outside as the output of this circuit.

In operation, when the input signal f _IN consists of a pulse train with a constant pulse width and period, the coincidence of logic levels between the input signal f _IN and the Q output of flip-flop 2 is detected by gate 1 and G input is energized. As a result, the counter 3 starts counting according to the clock signal f _c , and when it reaches a certain number of counts corresponding to the pulse width of the input signal f _IN in advance, the counter 3 starts counting by the clock signal f c .
With the output turned low, the R input is energized,
It will be reset. generated in this way
The OUT output pulse is output externally, and
It is supplied to flip-flop 2 and inverts the logic level of the Q output. Since the Q output is inverted, the inputs of gate 1 become inconsistent, and counter 3 stops counting. Count 3 is stopped until the logic level of the input signal f _IN is inverted and gate 1 detects coincidence of the logic levels again. Then, when a match is detected between the input signal f _IN and the Q output, the counter 3
Counting is restarted, and a pulse output signal f _OUT is generated from the OUT output at a constant count as described above.

In this way, pulses are output from the circuit in response to changes in the logic level of the input signal f _IN , so that these pulses form a pulse train with twice the frequency of the input signal f _IN .

If noise narrower than the pulse width of the input signal f _IN is superimposed on the input signal f IN , counter 3 will continue to count;
Since the count does not proceed until the OUT output becomes low, no pulse is output from the counter 3.

In addition, in the above embodiment, the case where the output to be taken out to the outside is obtained from the OUT output of the counter was explained.
It may also be the Q or output of a flip-flop, and the same effect as in the previous embodiment can be achieved.

As described above, according to this invention, the state of coincidence between the input signal and the Q output of the flip-flop is counted, and pulses are not output until a certain count is reached, so that pulses are not superimposed on the input signal. This can reduce the inconvenience of immediately outputting pulses due to noise.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional frequency doubler generating circuit, and FIG. 2 is a circuit diagram showing an embodiment of this invention. 1...Exclusive OR gate, 2...Flip gate
Flop, 3...counter. In addition, in the figures, the same reference numerals indicate the same parts.

Claims (1)

[Scope of utility model registration request] a flip-flop which performs binary operation according to an input pulse signal; a gate that detects a match in logic level between the output of the flip-flop and an input signal consisting of a pulse train; and an output from the gate that indicates the match. and a counter that counts the time of the signal and outputs the pulse signal when a certain count is reached.