JPS594336Y2 - digital integrator circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital integration circuit that receives signals from a plurality of signal generators.

Conventional digital integration circuits connect the signal from the signal generator directly to the clear terminal of the counter.

Therefore, when a plurality of signals are digitally integrated, a counter is prepared for each signal, or a counter is shared by taking the logical sum of all the signals to be digitally integrated.

The former method, in which a counter is prepared for each signal, is undesirable from the standpoint of circuit element implementation, and the latter method, in which a counter is shared by taking the logical sum of all signals, is a single signal because it takes the logical sum of all signals. There is a problem in that the digital integration effect for the signal is reduced when the signal reaches a level that disables counter clearing.

An object of the present invention is to eliminate the drawbacks of the prior art described above, and to enable digital integration of a plurality of signals efficiently in terms of implementation and reliably in terms of operation.

In the present invention, when performing digital integration of multiple signals, before taking the logical sum of each signal, the output of the flip-flop corresponding to each signal and this signal are taken, and then the independent digital integration of each signal can be performed. Focusing on the ability to perform multiple digital integrations, it was devised to utilize circuit elements effectively and reliably.

The present invention will be described below with reference to the drawings.

A plurality of signals to be digitally integrated are polarized in the same level direction, and the subsequent signals P1. A Nant gate 2 is provided which performs an AND operation between P2, . . . , Pn, and the output of the flip-flop 1 that stores the level of each signal.

The outputs of the respective Nant gates 2 are then logically summed and used as a clear input to the counter 3.

The frequency of the clock signal applied to the trigger input terminal of the counter 3 is set appropriately based on the integration time.
The output bits of can be freely selected from the integration time settings of each signal.

This selected output and the signal P1. P2. ..., P
A logical product with n is taken by a Nant gate 4, and the output of each Nant gate 4 is applied to the set input of each flip-flop 1.

Further, the reset input terminal of the flip-flop 1 is directly connected to each signal P1. P2. ..., Pn is added.

When another signal, for example Pl, changes from a low level to a high level, the clearing of the counter 3 becomes invalid and the clock signal starts counting.

If the integration time is set appropriately, it can be determined whether this signal level change is due to noise or an original level change.

That is, if it is due to noise, this change returns to the original level in a sufficiently short time compared to the integration time, making clearing the counter 3 effective.

Further, if the level change is an original one, the flip-flop 1 (Fl) that stores this signal level is set after the integration time has elapsed.

This output causes the Nandt gate 2 to close its gate and enable clearing of the counter 3, and the integration effect on the other signals P2 to Pn can be obtained in the same way.

FIG. 2 shows another embodiment of the present invention, in which the same parts as in FIG. 1 are designated by the same reference numerals.

The difference from FIG. 1 is that the reset input of the flip-flop 1 that stores the signal level also uses a digitally integrated output using the same configuration as the example of FIG. 1 above.

This embodiment is characterized in that it is possible to digitally integrate both high and low levels of a plurality of signals, and there is no need to convert the polarity of the signals as in the above embodiments.

In addition, in FIG. 2, 6 indicates each signal P, P2...,
This is an inverted gate that performs the logical product of Pn and the output of each flip-flop 1 corresponding to the signal, and generates a low level output when both inputs are at the low level.

7, similarly to the Nant gate 4 of the above embodiment, each signal P
1. P2. . . . An inverter gate 9 performs a logical AND operation between Pn and the output of the counter 8. 9 is an inverter.

As described above, according to the present invention, when performing digital integration of multiple signals, a counter can be shared, and in addition, it is possible to integrate a combination of human input signals that switch independently, or to perform integration for any one signal that is the starting point. It is possible to perform a reliable integration function for a group of input signals that have important meaning.

[Brief explanation of the drawing]

1 and 2 are block circuit diagrams showing embodiments of the digital integration circuit of the present invention, respectively. In the figure, 1 is a flip-flop, 2 and 4 are Nant gates, 3.8 is a counter, 5 is a resistor, 6 and 7 are invert Nant gates, and 9 is an inverter.

Claims (1)

[Scope of utility model registration request] A counter that counts clock signals and generates an output when the count value reaches a predetermined value, and at least as many signals as there are to be digitally integrated are provided, and each signal is ANDed with the output of the counter. first AND gates provided at least in number equal to the number of signals, and corresponding first AND gates;
Flip-flops having the output of the AND gate and the signal as set inputs and reset inputs, respectively; and at least as many flip-flops as the number of the signals, the flip-flops are provided to take the logical product of each signal and the output of the flip-flop corresponding to the signal. 2 logic gates, the output of the logical sum of each output of the second AND gate is used as a clear input of the counter, and the output of each of the flip-flops is used as a digital integration output of each of the signals. digital integration circuit.