JPS6376047A - Mode switching circuit for microprocessor - Google Patents

Abstract

PURPOSE:To prevent a package from being expanded by switching a mode in accordance with the length of a reset signal inputted from a reset terminal of a microprocessor (MPU). CONSTITUTION:At the time of inputting a reset signal, an overflow signal B is outputted through a reset pulse generating circuit 21 and an n-bit timer circuit 22 with a clear function and a signal C synchronized with the length of a reset signal inputted from the reset terminal of the MPU is outputted by a flip flop (FF) circuit 23a in a synchronizing shift register 23. If the reset signal inputted from the reset terminal of the MPU is a reset signal having the length decayed over a set period, an FF circuit 25 outputs a setting signal to switch a normal mode to a test mode and outputs an MPU operation start signal to start test mode operation. Consequently, the package including the MPU can be prevented from being expanded.

Description

[Detailed Description of the Invention] [Summary] Invented on Thursday, the microprocessor number has a built-in test circuit and a test mode switching circuit. Therefore, the mode of the microprocessor can be switched without increasing the number of terminals by changing the length of the reset signal input to the microprocessor.

[Industrial application field]

The present invention relates to a mode switching circuit for a microprocessor, and in particular, a test circuit and a test circuit for the microprocessor.
This invention relates to a mode switching circuit for a microprocessor that has a built-in test mode switching circuit.

[Conventional technology]

FIG. 4 is a diagram showing the configuration of a mode switching circuit of a conventional microprocessor.

In FIG. 4, 41 test circuits, 42 a test mode switching dedicated circuit, 431-j microprocessor, 44
The test mode switching signal input terminals are shown respectively.

The mode switching circuit of a conventional microprocessor is! By connecting the mode switching circuit 42 to the example using the test mode switching circuit shown in FIG. 4, mode switching from normal operation to test operation is performed.

[Problem that the invention seeks to solve]

However, conventional mode switching circuits for microprocessors have the disadvantage that the number of terminals increases because a new terminal dedicated to test mode switching is added to the microprocessor, and the package containing the microprocessor increases accordingly. Ta.

Therefore, it is an object of the present invention to provide a mode switching circuit for a microprocessor that has improved the above-mentioned problems.

[Means for solving problems]

FIG. 1 is a diagram showing the basic configuration of the present invention.

In the figure, numeral 1 is a counting means which receives a clock signal and a reset signal as input, and 2 is a test mode signal generating means which receives an output signal of the limb counting means C11 and a print reset signal as input.

Generally, in microprocessors and the like, a reset signal is used to initially clear internal registers, counters, etc. This reset signal is initially input to the microprocessor as a signal having a constant length for the above purpose.

The present invention focuses on this point, and increases the number of input terminals by inputting the above-mentioned reset signal to the microprocessor as a signal with a length different from the length of the predetermined reset signal determined for initial clearing during testing. This allows switching between test mode, t, qFi, and normal mode without having to do so.

That is, the mode switching circuit for a microprocessor according to the present invention includes a counting means 1 for counting the length of a reset signal inputted from a reset terminal of the microprocessor, and a counting means 1 for counting the length of a reset signal inputted from a reset terminal of the microprocessor. and a test mode signal generating means 2 for generating a test mode signal when a length exceeding the length is detected.

[Effect]

The present invention is constructed as described above, and in the microprocessor mode switching circuit according to the present invention, when a reset signal is input from the input terminal of the microprocessor, the counting means 1 calculates the length of this reset signal. A test mode signal is generated by the test mode signal seller means 2 when the counting means l detects that the time exceeds the time required to perform the initial clearing of the internal circuits of the microprocessor. .

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3.

FIG. 2 is a diagram showing one embodiment of the present invention.

FIG. 3 is a time chart explaining the operation timing of one embodiment of the present invention.

In FIG. 2, the same reference numerals as in FIG. 1 indicate the same objects.

In the figure, 21 indicates a counter clear pulse generation 00 path, a 22-digit clear n-bit timer circuit, 23 a synchronizing shift register, 24 an inverter, and a 25-digit flip-flop circuit.

Further, in this embodiment, the pit timer circuit 22 with a clear function is set to the number n of pits such that an over-70 signal is output for a long time in response to a reset signal of a predetermined length.

The operation in the normal mode will be described below using the operation time chart of FIG. 1a).

The counter clear pulse generating circuit 21 is composed of a plurality of inverters and NAND elements, and the counter clear pulse generating circuit 21 once changes from high level to low level as shown in Figure F3, and the n-bit timer circuit 22 with clear is input and the period is cleared, that is, it is cleared to zero.

Next, the n-bit timer circuit 22 with clear, that is, the n-stage 7-lip 70 dub circuits 22a to 22n, counts up the clock signal, and after the reset signal is input to the n-bit timer circuit 22 with clear, it is counted up by n times. At the point in time, the over 7a signal is output (third
Figure B). The reset signal is also input to the synchronization shift register 23 together with the clock signal, and the flip-flop circuit 23a in the measurement period shift register 23 outputs a reset signal synchronized with the clock signal.
Figure 3C). The running reset signal 9 inputted from the reset signal input terminal of the microprocessor is set by the n-bit timer circuit 22 with clear, and the reset is synchronized by the clock signal before reaching 9 o'clock open (overflow). If the length of the reset signal is such that the signal falls, the first circuit 25a will not be set and the signal C (E) in FIG. 3 indicating the normal mode will be output.

Further, the 7-rip, 70-tub circuit 23b in the synchronizing shift register 23 delays the signal shown in FIG. 3C by one clock (FIG. 3D), and outputs a start signal from the inverter 24, thereby starting normal operation.

Next, the switching operation to the test mode will be explained using the rbl operation time chart in FIG.

Similarly to the above, when a reset signal is input, an overflow signal (signal B) is outputted via the reset pulse generation circuit 21 and the n-pit timer circuit 22, and is inputted from the reset terminal of the microprocessor. A signal C synchronized with the length of the reset signal is outputted by the 7-lip, 70-tub circuit 23a in the synchronizing shift register 23.

At this time, if the 11 set signal inputted from the reset terminal of the microprocessor is a reset signal of such a length that it falls beyond the set time (overflow), the 1 clock circuit 25 pretends that the set signal is Output C Figure 3 (waveform E of bl) and switch to test mode.
Thereafter, in the same procedure as described above, an operation start signal (waveform F in FIG. 3 (bl)) of the microprocessor is outputted, and the test mode operation is started.

In addition, in this embodiment, a counter (
Although an example using a timer circuit has been described, it is also possible to use a one-shot multivibrator as the counting means.

〔Effect of the invention〕

As described above, the present invention is configured such that the mode switching circuit of the microprocessor switches the mode depending on the length of the reset signal input from the reset terminal of the microprocessor.

Therefore, it is possible to switch modes of the microprocessor without increasing the package size due to an increase in the number of terminals.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle configuration of the present invention, Fig. 2 shows an embodiment of the present invention, and Fig. 3 is an operation timing diagram of an embodiment of the present invention (at is the normal mode In the figure, 1... counting means, 2... ...Test mode signal generation means, 21...Counter clear pulse generation means, 22...
・N-bit tie with clear! Circuit, 23... Synchronization shift register, 41... Test circuit, 42... Test mode switching dedicated circuit, 43... Microprocessor,
44...Test mode switching signal input terminal.゛ , 4-] -7/' He - 43. My 70 Aro's death My 70 700 Zevry's 7-door beggar widening 1 circular road d-co purification 4 bacteria

Claims (1)

[Claims] In the mode switching circuit of the microprocessor, the microprocessor has a function of initially clearing the internal circuit by inputting a reset signal of a predetermined length to the reset terminal, and during testing, the microprocessor is inputted to the reset terminal as a signal having a length different from the predetermined length of the reset signal, and the mode switching circuit includes a counting means (1) for counting the length of the reset signal. , the counting means (1) is comprised of a test mode signal generating means (2) that generates a test mode signal when a length different from the predetermined length of the reset signal is detected. Features a microprocessor mode switching circuit.