JP2693798B2 - Control signal generation circuit - Google Patents
Control signal generation circuitInfo
- Publication number
- JP2693798B2 JP2693798B2 JP63305397A JP30539788A JP2693798B2 JP 2693798 B2 JP2693798 B2 JP 2693798B2 JP 63305397 A JP63305397 A JP 63305397A JP 30539788 A JP30539788 A JP 30539788A JP 2693798 B2 JP2693798 B2 JP 2693798B2
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- output
- control
- gate
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、デジタル信号処理の分野において制御の禁
止領域を持つ被制御部での制御信号変換発生回路に関す
るものである。Description: TECHNICAL FIELD The present invention relates to a control signal conversion generating circuit in a controlled portion having a control prohibited area in the field of digital signal processing.
従来、この種の回路は、制御信号の発生側に禁止領域
を知らせ、その禁止領域を避けた制御信号を発生するも
のとなつていた。Conventionally, this type of circuit has been designed to inform a generation side of a control signal of a prohibited area and generate a control signal avoiding the prohibited area.
〔発明が解決しようとする課題〕 上述した従来の方法では、制御部、被制御部間に制御
信号と禁止領域信号の２種の情報のやり取りが必要であ
つた。特に、集中制御において制御禁止領域を持つもの
が多数ある場合など、制御部に集まる情報が多くなつて
いた。[Problems to be Solved by the Invention] In the above-described conventional method, it is necessary to exchange two kinds of information, a control signal and a prohibited area signal, between the control unit and the controlled unit. In particular, in the case where there are many control prohibited areas in the centralized control, much information gathers in the control unit.
このような問題点を解決するため、本発明の制御信号
発生回路は、制御信号入力により出力信号の状態を変化
させる制御信号検出回路と、この制御信号検出回路の出
力信号の状態変化に基づいて制御信号を出力する制御信
号出力回路とを備え、さらに制御信号検出回路と制御信
号出力回路との間に自己保持回路が接続され、この自己
保持回路は、一方の入力端子が制御信号検出回路の出力
側に接続され出力端子が制御信号出力回路の入力側に接
続さてたオアゲートと、一方の入力端子が制御信号出力
回路の入力側に接続され出力端子がオアゲートの他方の
入力端子に接続されたアンドゲートとを備え、アンドゲ
ートは他方の入力端子から制御禁止領域信号が入力さ
れ、オアゲートの出力信号の状態は被制御部が制御禁止
領域にある間被制御部が制御禁止領域になる直前の状態
に保持されるものである。In order to solve such a problem, a control signal generation circuit of the present invention is based on a control signal detection circuit that changes a state of an output signal by a control signal input and a state change of an output signal of the control signal detection circuit. A control signal output circuit for outputting a control signal is further provided, and a self-holding circuit is further connected between the control signal detection circuit and the control signal output circuit. This self-holding circuit has one input terminal of the control signal detection circuit. An OR gate connected to the output side and having an output terminal connected to the input side of the control signal output circuit, and one input terminal connected to the input side of the control signal output circuit and the output terminal connected to the other input terminal of the OR gate AND gate, the AND gate receives the control prohibited area signal from the other input terminal, and the state of the output signal of the OR gate is controlled while the controlled section is in the control prohibited area. It is intended to be held in a state of immediately before the control prohibition region.
したがつて、本発明においては、制御信号がどのよう
なタイミングで送られてきても、受信側で制御禁止領域
を避けた制御信号に変換し発生することが可能になる。Therefore, in the present invention, no matter what timing the control signal is sent, the control signal can be generated by converting it into a control signal that avoids the control prohibited area on the receiving side.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明による制御信号発生回路の一実施例を
示す回路図である。この制御信号発生回路は被制御部の
一部分である。第１図に示すように、セット・リセット
形フリップフロップ（RS-FF）１のＱ出力端子およびAND
（アンド）ゲート３の出力端子がOR（オア）ゲート２の
２つの入力端子にそれぞれ接続され、ORゲート２の出力
端子およびANDゲート３の一方の入力端子がＤ形フリッ
プフロップ（D-FF）４のＤ入力端子に接続され、Ｄ形フ
リップフロップ４のＱ出力端子がＤ形フリップフロップ
５のＤ入力端子に接続され、Ｄ形フリップフロップ４の
出力端子およびＤ形フリップフロップ５のＱ出力端子
がNAND（ナンド）ゲート６の２つの入力端子にそれぞれ
接続されている。FIG. 1 is a circuit diagram showing an embodiment of a control signal generating circuit according to the present invention. This control signal generating circuit is a part of the controlled part. As shown in Fig. 1, the Q output terminal and AND of the set / reset type flip-flop (RS-FF) 1
The output terminal of the (AND) gate 3 is connected to the two input terminals of the OR gate 2, and the output terminal of the OR gate 2 and one input terminal of the AND gate 3 are D-type flip-flops (D-FF). 4 is connected to the D input terminal of D-type flip-flop 4, the Q output terminal of D-type flip-flop 4 is connected to the D input terminal of D-type flip-flop 5, and the output terminal of D-type flip-flop 4 and the Q output terminal of D-type flip-flop 5. Are connected to the two input terminals of the NAND gate 6, respectively.
また、セット・リセット形フリップフロップ１のリセ
ット（Ｒ）入力端子には制御部（図示せず）から制御信
号入力11があり、セット（Ｓ）入力端子には被制御部の
他の部分から制御終了信号12が入力され、ANDゲート３
の他方の入力端子には被制御部の他の部分から制御禁止
領域信号13が入力され、Ｄ形フリップフロップ4,5の各
クロック（CK）入力端子にはクロック14が入力され、NA
NDゲート６の出力端子から被制御部の他の部分に制御信
号が出力（制御信号出力15）される。Further, the reset (R) input terminal of the set / reset type flip-flop 1 has a control signal input 11 from a control section (not shown), and the set (S) input terminal controls from other parts of the controlled section. End signal 12 is input and AND gate 3
A control prohibited area signal 13 is input to the other input terminal of the controlled part from the other part of the controlled portion, and a clock 14 is input to each clock (CK) input terminal of the D-type flip-flops 4 and 5.
A control signal is output (control signal output 15) from the output terminal of the ND gate 6 to the other part of the controlled part.
なお、セット・リセット形フリップフロップ１は制御
信号検出回路として機能し、制御信号入力11によりその
出力信号の状態を変化させる。また、Ｄ形フリップフロ
ップ回路4,5およびNANDゲート６は制御信号出力回路を
構成しており、セット・リセット形フリップフロップ１
の出力信号の状態変化に基づいて制御信号を出力する。
また、ORゲート２およびANDゲート３は自己保持回路を
構成しており、被制御部が制御禁止領域にある間、その
出力信号の状態を被制御部が制御禁止領域になる直前の
状態に自己保持する。The set / reset type flip-flop 1 functions as a control signal detection circuit, and changes the state of its output signal by the control signal input 11. Further, the D-type flip-flop circuits 4 and 5 and the NAND gate 6 constitute a control signal output circuit, and the set / reset-type flip-flop 1
The control signal is output based on the state change of the output signal of the.
Further, the OR gate 2 and the AND gate 3 compose a self-holding circuit, and while the controlled unit is in the control prohibited area, the output signal state is changed to the state immediately before the controlled unit becomes the control prohibited area. Hold.
ここで、第２図（ａ）〜（ｈ）および第３図（ａ）〜
（ｈ）に、それぞれクロツク14,制御禁止領域信号13,制
御信号入力11および各部の出力のタイミングチヤートを
示し、第２図は入力される制御信号11が制御禁止領域に
ない場合を、第３図は入力される制御信号11が制御禁止
領域にある場合を示している。Here, FIGS. 2 (a) to (h) and FIG. 3 (a) to
(H) shows the timing chart of the clock 14, the control prohibited area signal 13, the control signal input 11 and the output of each part. FIG. 2 shows the case where the input control signal 11 is not in the control prohibited area. The figure shows the case where the input control signal 11 is in the control prohibited area.
上記実施例の回路構成において、第２図（ｃ）に示す
ように入力される「Ｌ」の制御信号11が第２図（ｂ）に
示す禁止領域（制御禁止領域信号13が「Ｈ」の部分）に
ない場合には、各フリツプフロツプ1,ORゲート2,フリツ
プフロツプ４および５は第２図（ｄ）〜（ｇ）に示す如
く動作し、第２図（ｃ）に示す制御信号11が入力された
時点で、NANDゲート６から第２図（ｈ）に示す制御信号
出力15が発生される。しかし、第３図（ｃ）に示すよう
に入力された「Ｌ」の制御信号11が第３図（ｂ）の禁止
領域（「Ｈ」の部分）にある場合には、各フリツプフロ
ツプ1,ORゲート2,フリツプフロツプ４および５は第３図
（ｄ）〜（ｇ）に示す如く動作し、その禁止領域をはず
れるまで待つてからNANDゲート６より第３図（ｈ）に示
す制御信号出力15が発生されることになる。また、一度
制御信号入力を受付後は、制御終了信号12が入力される
まで次の入力を受付けないものとなつている。したがつ
て、本実施例によると、制御信号入力11がどのようなタ
イミングで送られてきても、受信側で制御禁止領域を避
けた制御信号出力15に変換し発生することができる。In the circuit configuration of the above-described embodiment, the control signal 11 of "L" input as shown in FIG. 2 (c) is the prohibited area (control prohibited area signal 13 is "H") shown in FIG. 2 (b). 2), the flip-flop 1, the OR gate 2, and the flip-flops 4 and 5 operate as shown in FIGS. 2D to 2G, and the control signal 11 shown in FIG. 2C is input. At that time, the NAND gate 6 generates the control signal output 15 shown in FIG. 2 (h). However, when the control signal 11 of "L" input as shown in FIG. 3 (c) is in the prohibited area ("H" portion) of FIG. 3 (b), each flip-flop 1, OR The gate 2, flip-flops 4 and 5 operate as shown in FIGS. 3 (d) to (g), and wait until the gate goes out of the prohibited area, and then the NAND gate 6 outputs the control signal output 15 shown in FIG. 3 (h). Will be generated. Further, once the control signal input is received, the next input is not received until the control end signal 12 is input. Therefore, according to this embodiment, no matter what timing the control signal input 11 is sent, it can be generated by converting it to the control signal output 15 avoiding the control prohibited area on the receiving side.
なお、本発明は上述の実施例にのみ限定されるもので
はなく、特許請求の範囲に記載された範囲内において種
々変更し得るものである。It should be noted that the present invention is not limited to the above-described embodiments, but can be variously modified within the scope of the claims.
以上説明したように本発明は、任意のタイミングで送
られてくる制御信号を制御禁止領域を避けたものに変更
することにより、制御禁止領域を持つ被制御部に対し、
制御部がその制御禁止領域を意識することなく、制御信
号を発生することができる効果がある。As described above, the present invention, by changing the control signal sent at an arbitrary timing to avoid the control prohibited area, to the controlled portion having the control prohibited area,
There is an effect that the control unit can generate the control signal without being aware of the control prohibited area.
第１図は本発明の一実施例を示す回路構成図、第２図お
よび第３図は上記実施例の動作説明に供するタイミング
チヤートである。 １……セツト・リセツト形フリツプフロツプ、２……OR
ゲート、３……ANDゲート、4,5……Ｄ形フリツプフロツ
プ、６……NANDゲート。FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are timing charts for explaining the operation of the above embodiment. 1 ... Set / Reset type flip-flop, 2 ... OR
Gate, 3 ... AND gate, 4,5 ... D-type flip-flop, 6 ... NAND gate.
フロントページの続き (56)参考文献 特開 昭60−137121（ＪＰ，Ａ) 特開 昭60−244113（ＪＰ，Ａ)Continuation of the front page (56) References JP-A-60-137121 (JP, A) JP-A-60-244113 (JP, A)
Claims (1)
させる制御信号検出回路と、 この制御信号検出回路の出力信号の状態変化に基づいて
制御信号を出力する制御信号出力回路とを備え、 さらに、前記制御信号検出回路と前記制御信号出力回路
との間に自己保持回路が接続され、 この自己保持回路は、 一方の入力端子が前記制御信号検出回路の出力側に接続
され、出力端子が前記制御信号出力回路の入力側に接続
されたオアゲートと、 一方の入力端子が前記制御信号出力回路の入力側に接続
され、出力端子が前記オアゲートの他方の入力端子に接
続されたアンドゲートとを備え、 前記アンドゲートは、他方の入力端子から制御禁止領域
信号が入力され、 前記オアゲートの出力信号の状態は、被制御部が制御禁
止領域にある間、前記被制御部が制御禁止領域になる直
前の状態に保持されることを特徴とする制御信号発生回
路。1. A control signal detection circuit for changing a state of an output signal by inputting a control signal, and a control signal output circuit for outputting a control signal based on a state change of an output signal of the control signal detection circuit. A self-holding circuit is connected between the control signal detection circuit and the control signal output circuit. In this self-holding circuit, one input terminal is connected to the output side of the control signal detection circuit and the output terminal is An OR gate connected to the input side of the control signal output circuit, and an AND gate having one input terminal connected to the input side of the control signal output circuit and an output terminal connected to the other input terminal of the OR gate. The AND gate receives a control prohibited area signal from the other input terminal, and the state of the output signal of the OR gate indicates that the controlled portion is in the controlled prohibited area. A control signal generation circuit characterized in that the control section is held in a state immediately before the control section becomes a control prohibited area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63305397A JP2693798B2 (en) | 1988-12-02 | 1988-12-02 | Control signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63305397A JP2693798B2 (en) | 1988-12-02 | 1988-12-02 | Control signal generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02151116A JPH02151116A (en) | 1990-06-11 |
| JP2693798B2 true JP2693798B2 (en) | 1997-12-24 |
Family
ID=17944630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63305397A Expired - Lifetime JP2693798B2 (en) | 1988-12-02 | 1988-12-02 | Control signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2693798B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60137121A (en) * | 1983-12-26 | 1985-07-20 | Nec Corp | Chattering preventing circuit |
| JPS60244113A (en) * | 1984-05-18 | 1985-12-04 | Hitachi Ltd | Waveform shaping circuit |
-
1988
- 1988-12-02 JP JP63305397A patent/JP2693798B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02151116A (en) | 1990-06-11 |
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