JPH0376421A - 2-clock switching circuit - Google Patents

Abstract

PURPOSE:To prevent a leading edge due to a select signal from generating by switching a clock immediately when a selected clock signal is at an L level when a select signal is switched, and switching the clock after the selected clock signal reaches an L level when the selected clock signal is at an H level. CONSTITUTION:When a clock signal is switched from CKA into a clock signal CKB, an SR latch 9 is reset, an output f3 goes to an L level and an H level is outputted from a NAND gate 11. When the clock signal CKB is at an L level at that time, an SR latch 10 is set and an inverse of the clock signal CKB is outputted immediately from a NAND gate 12. When the clock signal CKB is at an H level, a HAND gate 8 goes to an H level after the clocks signal CKB reaches an L level to set the SR latch 10. Then the clock signal CKB is outputted to a clock output 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a selector circuit that switches between two clocks.

[Prior Art] FIG. 4 is a circuit diagram showing a conventional two-clock switching circuit. In the figure, 1 is an input terminal to which one clock input CKA is input, 2 is an input terminal to which the other clock input CKB is input, 3 is an input terminal to which the select signal S of 2 clocks is input, and 6 is an inverter. , 11, 12, 1
3 and 15 are NAND gates, 14 is clock human power CKA,
This is an output terminal for a clock output signal CKO selected by either CKB or the select signal S and output.

Next, the operation will be explained. FIG. 5 is a time chart showing the operation of the circuit of FIG. 4. In the figure, (al is clock input CKA, (bl is clock input CKB,
(cl indicates the select signal S, and (d) indicates the clock output signal CKO. Also, 16.17 indicates a rising edge generated in CKO due to a change in the select signal S, and 18 indicates a spike.

When the 2-clock select signal S is at the L level, the output of the inverter 6 is at the H level, so the NAND gate outputs the inverse signal of the clock signal CKA, and the NAND gate 12 outputs the H level, so the NAND gate 13 outputs a clock signal C. Conversely, when the 2-clock select signal S is at H level, the output of inverter 6 is at L level, so NAND gate 1
1 outputs an H level, and the NAND gate 12 outputs an inverted signal of the clock signal CKB, so the NAND gate 13 outputs the clock signal CKB.

In other words, when the select signal S is at L level, the clock signal C
When KA is at H level, a clock signal CKB is output to the clock output terminal 14.

The NAND gate 15 is a gate provided to prevent spikes, and when the two clocks CKA and CKB are both at the H level, the select signal S changes from the H level to the L level.
When switching to level, due to the delay of inverter 6,
-For a moment, both the NAND gate 11 and 120 outputs become H level, and the clock output signal CKOKL spikes 18.
This is to prevent this from occurring. nand gate 1
5 outputs L when the two clock inputs CKA and CKB are both at H level, so when the select signal is switched, -for an instant.

Even if the outputs of the NAND gates 11 and 12 are both at H level, the spike 18 can not be generated in the clock output signal CKO.

[Problem to be solved by the invention]

Since the conventional two-clock switching circuit is configured as described above, the two clocks CKA and CKB are input to the clock output signal CKO depending on the change in the select signal S.
Rising edges other than the rising edges of 16.17
Therefore, when the clock output signal CKO is connected to the clock input of a positive edge sense flip-flop, the flip-flop operates at a timing other than the rising edge of the original clock CKA and CKB. was there.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a two-clock switching circuit that can prevent rising edges other than those caused by the original clock input by switching the select signal from occurring. shall be.

[Means to solve the problem]

The two-clock switching circuit according to the present invention includes a NAND gate and an inverter for determining whether the selected clock signal is at L level or H level when the select signal is switched, and their output signals. This is equipped with an SR clutch that receives and generates switching timing.

[Effect]

In the two-clock switching circuit of the present invention, when the select signal is switched, the selected clock signal is low.
It is determined whether the clock is at the low level or the high level, and if the clock is at the low level, the clock is switched immediately, and if the clock is at the high level, the clock is switched after the clock reaches the low level.

〔Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a two-clock switching circuit according to the present invention. In the figure, the numbers 1 to 3.6.12
.about.14 are the same as the conventional ones, and their explanation will be omitted. 4 and 5 have inverters, 7.8 has a two-man powered NAND gate, and 9.10 has an SR clutch.

Next, the operation will be explained.

When the select signal S is at L level, the Q output signal f3 of SR clutch 9 is at H level, and the Q output signal f of SR clutch 0 is
4 is at the L level, the clock signal CKA is output from the NAND gate 13, and the clock output terminal 1
It is output to 4.

When the select signal S is switched from the L level to the H level, that is, the clock signal is switched from CKA to CKB, the SR clutch is reset, f3 becomes the L level, and the NAND gate 11 outputs the H level. If clock signal CKB is at L level at that time, the output of inverter 5 is at H level, so the output of NAND gate 8 is at L level and SR clutch 0 is set. Then, f4 becomes H level, so the inverted signal of the clock signal CKB is immediately output from the NAND gate 12, and the clock signal CKB is outputted to the clock output 14 through the NAND gate B.

Furthermore, if the clock signal CKB is at the H level when the select signal S is switched from the L level to the H level, the output of the inverter 5 is at the L level, so the output of the NAND gate 8 does not immediately go to the H level. clock signal CK
After B becomes L level, NAND gate 8 becomes H level and SR clutch 0 is set. Then, the clock signal CKB is outputted to the clock output 14.

When the select signal S is switched from H level to L level, SR clutch 0 is reset and SR latch 9
The timing of setting is controlled.

FIG. 2 is a time chart showing the operation of FIG. 1. In the figure, (at is the clock input CKA, (bl is the clock input CKB, (cl is the select signal S, (dl
The clock output signal CKO1(e) is the output f1 of the NAND gate 7, (0 is the output signal f2 of the NAND gate 8,
(gl indicates the Q output f3 of the SR latch 9, and (h) indicates the Q output of the SR clutch 0. Also, 19 to 22 indicate changing points of the select signal S.

As can be seen from this time chart, when the select signal changes at 20.21, the selected clock signal is at L level at that time, so as the select signal changes, f
3, f4 becomes H level and a clock signal is output.

In the change of the select signal in 19.22, the selected clock signal is at H level at that time, so even if the select signal changes, f3. f4 does not go to H level, and when the selected clock signal goes to L level, K, f3, f
4 becomes the rHJ level, and a clock signal is output.

In the above embodiment, a case has been described in which the clock output terminal 14 is connected to the clock input of a positive edge sense flip-flop, but even in the case of a negative edge sense flip-flop, the change in the select signal S causes the original clock signal to be changed. If a falling edge other than the one shown in FIG. 3 occurs, it would be a problem, so by creating a circuit as shown in FIG. 3, the same effect as in the above embodiment can be achieved.

Note that numerals 1 to 12 and 14 in FIG. 3 are the same as those shown in the above embodiment, and 23 is an AND gate.

〔Effect of the invention〕

As described above, according to the present invention, by configuring the 2-clock switching circuit with an inverter, a NAND gate, and an SR latch, when the select signal is switched, the selected clock signal is either at L level or at H level. If the clock is at L level, the clock is switched immediately, and if it is at H level, the clock is switched after it becomes L level. Therefore, a two-clock switching circuit that does not generate a rising edge due to the select signal is obtained. There is an effect that can be done.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a two-clock switching circuit according to the present invention, FIG. 2 is a time chart showing the operation of the circuit of FIG. 1, and FIG. FIG. 4 is a circuit diagram showing a conventional two-clock switching circuit, and FIG. 5 is a time chart showing the operation of the circuit shown in FIG. 4. 1.2.3... Input terminal, 4, 5.6... Inverter, 7, 8, 11, 12.13... NAND gate, 9.10... SR latch, 14... Output terminal ,2
3...and gate. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a two-clock switching circuit that switches two clocks using a select signal, when the select signal is switched, it is determined whether the selected clock signal is at L level or H level.
A NAND gate and an inverter for determining the level, an SR latch for receiving their output signals and generating switching timing, and an output and a
receives two clock signals and generates a clock output signal 3
A two-clock switching circuit characterized by having two NAND gates.