JPH02124627A - Clock driver circuit - Google Patents

Abstract

PURPOSE:To select a delay time of a mutual change point of complementary signals with respect to a clock input freely by providing 2 delay time selection circuits. CONSTITUTION:The circuit consists of 2-input NOR logic circuits 4, 7, an inverter 10, and delay time selection circuits 5, 8. In this case, if the input signal changes to a high level, the output of the inverter 10 goes to a low level and the level of the 1st output terminal 2 goes to a low level. Since the low output is delayed via the circuit 5 and inputted to the 2-input NOR 7, the level of the 2nd output terminal 3 changes from a low to a high level. When the input signal changes to a low level, the output of the inverter 10 goes to a high level and the level at the terminal 3 goes to a low level. The low level output is delayed via the circuit 8 and inputted to the 2-input NOR circuit 4, then the level of the terminal changes from a low to a high level. Thus, complementary clocks whose high level is not overlapped with respect to the input clock are outputted because of the delay time of the circuits 5, 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock driver circuit, and particularly to a clock driver circuit that generates clock pulses that do not overlap with each other in a synchronous sequential circuit, a DAC circuit, or the like.

[Conventional technology]

Such a conventional clock driver circuit uses a NOR logic circuit inverter circuit and a delay circuit to create complementary clocks and the like.

FIG. 7 is a block diagram of a clock driver circuit showing an example of such a conventional clock driver circuit.

As shown in Figure 7, this clock driver circuit consists of two
human-powered NOR logic circuits 4 and 7, an inverter 10,
It is composed of delay circuits 23 and 24 that delay the output clocks of these logic circuits 4 and 7, and extracts a complementary clock whose phase is inverted from the clock from the input terminal 1 from the first output terminal 2, and outputs a complementary clock whose phase is inverted from the clock from the input terminal 1. This circuit extracts a delayed clock from the output terminal 3. Here, the delay time of the delay circuits 23 and 24 is set to a sufficiently larger value than the delay time of the gate stage.

FIG. 8 is a signal waveform diagram for explaining the operation of the clock driver circuit shown in FIG. 7.

As shown in FIG. 8, first, when the clock input signal is in a low state, that is, when the input terminal 1 is in a low state, the outputs of the inverter 10, the second input terminal N0R4, and the delay circuit 23 are in the high state, and the outputs of the second input terminal N0R7 and the delay circuit are in the high state. The output of 24 is in a low state. Next, when the input signal changes from a low state to a high state, the output of the inverter 10 becomes a low state, and the output of the two-man power N0R4, that is, the first output terminal 2, also becomes a low state. When this low output is delayed through the delay circuit 23 and input to the two-man power N0R7, the two-man power N0R
7, that is, the second output terminal 3 changes from a low state to a high state. Next, when the input signal changes from a high state to a low state, the output of the inverter 10 becomes a high state, and the output of the two-power N0R7, that is, the second output terminal 3
goes from high to low. This low output is the delay circuit 2
When delayed through 4 and input into 2-man power N0R4, 2
The output of the human power N0R4, that is, the first output terminal 2 changes from the low state to the how state. In this way, complementary clocks whose high states do not overlap by the delay time of the delay circuit 23 or 24 can be output to the first output terminal 2 and the second output terminal 3.

[Problem to be solved by the invention]

The conventional clock driver circuit described above has the drawback that the time difference between the changing points of complementary clock outputs can only be delayed by a certain value due to the delay circuit, and that it becomes difficult to select the clock when incorporated into a semiconductor integrated circuit. There is.

An object of the present invention is to provide a clock driver circuit that can change the delay time of such complementary clocks.

[Means to solve the problem]

The clock driver circuit of the present invention is a clock driver circuit that takes out a complementary clock signal of a clock signal, and has a first input terminal connected to a clock input terminal and a first clock output terminal connected to a first clock output terminal. a logic circuit; an inverting circuit having an input terminal connected to the clock input terminal; and a second inverting circuit having a first input terminal connected to the output terminal of the inverting circuit and having an output terminal connected to a second clock output terminal. a logic circuit having an input terminal and an output terminal connected to the output terminal of the first logic circuit and the second input terminal of the second logic circuit, respectively, and having at least one control terminal, and selecting a delay time. a first delay time selection circuit having an input terminal and an output terminal connected to an output terminal of the second logic circuit and a second input terminal of the first logic circuit, respectively, and having at least one control terminal; and a second delay time selection circuit that can select the delay time.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a clock driver circuit showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment consists of two N0Rs 4 and 7, an inverter 10, and a delay time selection circuit 5.8 each having a control terminal 6.9. is output from the first output terminal 2 and the second output terminal 3 as complementary clocks. Incidentally, the delay times selected by these delay time selection circuits 5.8 are set to values sufficiently larger than the delay time of one stage of gates, as in the above-mentioned conventional example.

FIG. 2 is a signal waveform diagram for explaining the operation of the clock driver circuit shown in FIG. 1.

As shown in FIG. 2, when the clock input signal is in a low state, that is, the input terminal 1 is in a low state, the inverter 1
0. Each output of the first two-manpower N0R4 and the first delay time selection circuit 5 is in a high state, and the second two-manpower N0R7
and the respective outputs of the second delay time selection circuit 8 are in the low state. Next, when the input signal changes to a high state, the output of the inverter 10 becomes a low state, and the output of the two-man power N0R4, that is, the first output terminal 2 becomes a low state. This low output is delayed via the delay time selection circuit 5 and
7, the output of the two-man power N0R7, that is, the second output terminal 3 changes from a low state to a high state.

Next, when the input signal changes to a low state, inverter 1
0 becomes a high state, and the output of the two-man power N0R7, that is, the second output terminal 3 becomes a low state. This low output is delayed through the delay time selection circuit 8 and
4, the output of the two-man power N0R4, that is, the first output terminal 2 changes from the low state to the high state.

In this way, the first output terminal 2 and the second output terminal 3
It is possible to output a complementary clock whose high state does not overlap with the input clock by the delay time of delay time selection circuits 5 and 8, respectively.

FIG. 3 is a configuration diagram showing an example of the delay time selection circuit shown in FIG. 1.

As shown in FIG. 3, the delay time selection circuit 5 or 8 is connected to a first delay circuit 13 connected to the input terminal 11, and to a circuit that short-circuits this delay circuit 13 and the delay circuit 13. a second delay circuit 14 connected to the switch 16; a second switch 17 connected to the delay circuit 14 and a circuit shorting the delay circuit 14; It is comprised of a third delay circuit 15 connected between the output terminal 12 and a decoder circuit 18 for controlling the switches 16 and 17 based on the control signal from the control terminal 9. The switch 16 or 17 is controlled by the decoded output 19 and 20 inputted to the decode circuit 18 and decoded.

FIG. 4 is a signal waveform diagram for explaining the operation of the delay time selection circuit shown in FIG. 3.

As shown in FIG. 4, this signal waveform is (a) to (C) at the output terminal 12 in response to the clock input to the input terminal 11.
It represents the states of three clock outputs.

For example, as shown in FIG. 4, when the switches 16 and 17 both close the lower path, the signal input to the input terminal 11 passes only through the delay circuit 15 and is delayed as shown in the clock output (a). and is output to the output terminal 12. Similarly, the input value of the control signal 9 controls the switches 16 and 17 via the decoder circuit 18, resulting in a clock output (b).

The delayed output can be taken out from the output terminal 12 as shown in (c).

FIG. 5 is a block diagram of a clock driver circuit showing a second embodiment of the present invention.

As shown in FIG. 5, this embodiment differs from the first embodiment described above in that a two-man NAND 21 is used as the first logic circuit, and a two-man NAND 22 is used as the second logic circuit. The points are the same.

FIG. 6 is a signal waveform diagram for explaining the operation of the clock driver circuit shown in FIG. 5.

As shown in FIG. 6, when the input signal from the input terminal 1 is in a low state, the output of the two-man NAND 21 and the inverter 1
Since the output of 0 is in a high state and the output of the delay time selection circuit 5 is also in a high state, both of the two NANDs 22 are in a high state, and this output is in a low state. Next, when the input signal changes to a high state, the inverter 10
The output of the NAND 22 changes to a low state, and the output of the two-man power NAND 22, that is, the second output terminal 3 becomes a high state.

This low output is delayed via the delay time selection circuit 8,
Since it is input to 2-man power NAND21, 2-man power NAND
21, that is, the output from the first output terminal 2 changes from a high state to a low state. Next, when the input signal changes from a high state to a low state, the output of the inverter 10 becomes a high state, and the output of the two-man power NAND 21, that is, the output of the first output terminal 2 changes from a low state to a high state. Since this high output is delayed through the delay time selection circuit 5 and input to the two-man NAND 22, the output of the two-man NAND 22, that is, the output of the second output terminal 3 changes from a high state to a low state.

In this way, the first output terminal 2 and the second output terminal 3
In this case, it is possible to output a complementary clock whose low state does not overlap with the input clock by the delay time of the delay time selection circuit 5 or 8.

〔Effect of the invention〕

As explained above, the clock driver circuit of the present invention has two delay time selection circuits that can change the delay time using their respective control terminals, thereby delaying the mutual change points of complementary output signals relative to the clock input. This has the effect of allowing you to freely choose your time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a clock driver circuit showing a first embodiment of the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of the clock driver circuit shown in FIG. 1, and FIG.
1 is a block diagram showing an example of the delay time selection circuit shown in FIG. 1, FIG. 4 is a signal waveform diagram for explaining the operation of the delay time selection circuit shown in FIG. 3, and FIG. 6 is a signal waveform diagram for explaining the operation of the clock driver circuit shown in FIG. 5; FIG. 7 is a clock driver circuit diagram showing a conventional example; FIG. 8 is a signal waveform diagram for explaining the operation of the clock driver circuit shown in FIG. 7. 1... Input terminal, 2... First output terminal, 3...
Second output terminal, 4, 7...NOR logic circuit, 5.8
... Delay time selection circuit, 6, 9... Control terminal, 10
...Inverting circuit (inverter), 11...Input terminal, 1
2... Output end, 13-15... Delay circuit, 16.1
7... Switch, 18... Decoder circuit, 19.2
0...Decoder output, 21.22...NAND logic circuit. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In a clock driver circuit that takes out a complementary clock signal of a clock signal, a first logic circuit whose first input terminal is connected to the clock input terminal and whose output terminal is connected to the first clock output terminal; and the clock input terminal a second logic circuit whose first input terminal is connected to the output terminal of the inversion circuit and whose output terminal is connected to a second clock output terminal; a first delay time selection circuit whose output terminals are connected to the output terminal of the first logic circuit and the second input terminal of the second logic circuit, respectively, and has at least one control terminal and is capable of selecting a delay time; and a second logic circuit whose input terminal and output terminal are respectively connected to the output terminal of the second logic circuit and the second input terminal of the first logic circuit, and which has at least one control terminal and is capable of selecting a delay time. A clock driver circuit comprising: a delay time selection circuit;