JPS63245010A - Multiplying circuit - Google Patents

Abstract

PURPOSE:To generate a 2-multiple clock excellent in duty by selecting a delay clock extracted in response to the position of a delay clock phase-shifted by a phase of 1/2 period or over of an input clock in a phase detection delay circuit section. CONSTITUTION:A selector control signal corresponding to the extracted position of the phase detection delay clock having a phase exceeding the phase of the input clock CK detected at a phase detection section 6 at first by a 1/2 period of the clock in the extracted position of a phase detection delay circuit section 5 is outputted from the phase detection section 6 to a selector 7. Thus, A delay clock CKD3 is selected when the operating time of the inverter in, e.g., a delay circuit section 1 is faster in response to the selector control signal outputted from the phase detection section 6, then the delay clock CKD 3 is selected by the selector 7, and when the operation time of the inverter is slow, the delay clock CKD1 is selected. Thus, the clock CK2F having a double frequency is outputted to an output terminal 4 to generate a 2 multiple clock excellent in duty.

Description

Detailed Description of the Invention (Summary) In a transmitting circuit of an integrated circuit that uses a delay circuit using a delay gate circuit and an exclusive OR circuit to order a clock of twice the frequency, the delay is A of the input clock. A delay circuit unit that outputs a delayed clock from a position whose phase is shifted by a period and a position ±n from the position, a phase detection delay circuit unit that outputs a two-phase detection clock, and an A period of the input clock. a phase detection unit that detects a phase detection clock with a phase shift of more than 1 minute;

a selector for selecting a delay clock of the delay circuit section;
An exclusive OR circuit is provided that generates a doubled clock from the delayed clock selected by the selector and the original input clock, and the pulse width of the generated doubled clock is determined by using the phase detection section. It is designed to stay within the range.

[Industrial application field]

The present invention relates to a multiplier circuit, particularly a multiplier circuit for large integrated circuits.

[Conventional technology]

In the field of communications, the frequency of the 9 input clock is doubled to create 2, for example CM I (Code Mark Inve
rsion) is used in the encoder circuit. In this case, a delay line may be used to delay the clock, but from the perspective of cost reduction, this method is not a good idea, and it is not advisable to use an easy-to-manufacture delay element9, such as an inverter, on the integrated circuit. It is required to form and realize.

5 and 6 (A) and (B) show the conventional multiplier circuit configuration and its time chart.
1.1-2. ...1-N is an inverter.

2 represents an exclusive OR circuit, 3 represents an input terminal, and 4 represents an output terminal.

The clock GK input to the input terminal 4 is delayed by the propagation delay times of the even number of inverters 1-1 to 1-2N as shown in FIG. 6(A)(ii). When the delayed clock CKD and the original input clock CK are subjected to an exclusive OR in the exclusive OR circuit 2, the result shown in FIG. 6(A)(ii)
As shown in the figure, a clock CK2F having twice the frequency of the input clock CK is output to the output terminal 4.

[Problem that the invention seeks to solve]

In the conventional circuit configuration as shown in FIG.

The delay time caused by inverters 1-1 to 1-2N is the number of inverters that delay the phase of the input clock CK by two cycles (an even number of inverters is selected for its operation), based on the standard operating time of one inverter. Even if the propagation delay time of each inverter manufactured on an integrated circuit is within the standard value, the propagation delay time of inverters 1-1 to 1-2N varies depending on the manufactured integrated circuit. There are variations in the duty of the obtained double clock clock CK2F, which is necessary to operate the secondary stage flip-flop circuit, etc., and does not meet the lock width standards, etc.2
There was a drawback that the multiplied clock CK2F was generated.

FIG. 6(B) is a time chart of the double clock CK2F when the delay time of inverters 1-1 to 1-2N is 0.5 times faster than the standard delay time of FIG. 6(A). The pulse width of the ``level'' becomes narrower and becomes less than the minimum pulse width on the ``H'' side necessary to operate the flip-flop circuit, etc. of the primary stage, and the flip-flop circuit etc. no longer operate.

Conversely, even when the delay time of inverters 1-1 to 1-2N is slower than the standard delay time shown in FIG. 6(A), the pulse width of the obtained doubled clock becomes narrower, As expected, flip-flop circuits etc. do not operate.

Therefore, even if the propagation delay time of each inverter 1-1 to 1-2N varies due to manufacturing, the transmitter can always generate a double clock with excellent duty so that the integrated circuit will not become defective. circuit is desired.

[Means for solving problems]

FIG. 1 shows a basic configuration diagram of a multiplier circuit according to the present invention, in which 1 represents a delay circuit section, 5 a phase detection delay circuit section, 6 a phase detection section, and 7 a selector. Numbers 2 to 4 correspond to the figures in Figure 5.

The delay circuit section 1 is a gate circuit that is easy to manufacture using an integrated circuit, such as an inverter, and is a circuit that delays the input clock CK input to the input terminal 3. The delay circuit section 1 is a gate circuit that is easy to manufacture using an integrated circuit, for example, and is a circuit that delays the input clock CK input to the input terminal 3. C.K.D.
2. The configuration is such that each CKD3 is extracted.

The delayed clock CKD2 is extracted from the positions of an even number of inverters whose phases are theoretically shifted by A period of the input clock input to the input terminal 3, and the delayed clock CKD2 is
D1 is extracted from the position of the inverter two places before it, and delayed clock CKD3 is extracted from the position of the inverter two places after it.

The phase detection delay circuit section 5 is a delay circuit for obtaining a clock obtained by further delaying the clock delayed by the delay circuit section 1 using two inverters.

This circuit generates a delayed clock for phase detection for detecting a delayed clock whose phase is shifted by two cycles or more of the input clock CK in the phase detecting section 6, which will be described next.

The phase detection section 6 is a detection circuit that detects a delayed clock whose phase is shifted by A period or more of the input clock CK based on the phase detection delay clock outputted from the phase detection delay circuit section 5, and the phase Delayed clocks GKDI, CKD2 extracted from the delay circuit section 1 according to the extracted position in the phase detection delay circuit section 5 of the detection delay clock
．． This is a selector control signal generation circuit that selects one of CKD3.

[Effect]

The input clock CK input to input terminal 3 is.

The delayed clocks CKD1 to CKD2 are delayed by the delay circuit l and input to the selector 7. At this time, it may be considered that the clocks whose phase is delayed by A period of the input clock CK are normally distributed around the delay clock CKD2 of the delay circuit section 1 due to the manufacturing of the integrated circuit.

On the other hand, the delay clock CK is output from the two-phase detection delay circuit section 5.
Delayed clocks for phase detection that further delay D3 are generated as shown in the figure, and if any of these delayed clocks for phase detection generates a delayed clock that exceeds the phase of A cycle of input clock CK. These phase detection delay clocks generated in the 0 phase detection delay circuit section 5 are examined in order from the leftmost clock in the figure in order to first exceed the phase of A period of the input clock CK in the 1 phase detection section 6. A phase detection delay clock having a phase (exceeding) is detected. Input clock CK detected by the phase detection section 6
A selector control signal corresponding to the extraction position in the phase detection delay circuit section 5 of the phase detection delay clock having a phase that first exceeds the phase of two cycles of is outputted from the phase detection section 6 to the selector 7. Ru. Thereby, the selector 7 responds to the selector control signal output from the phase detection section 6.

For example, when the operating time of the inverter forming the delay circuit section l is fast, the delayed clock CKD3 is selected, and conversely, when the operating time of the inverter forming the delay circuit section l is slow, the delayed clock CKD1 is selected.

In this way, the delay clocks CKD L to CKD3 are selected according to the actual operating time of the inverter in the delay circuit section 1.
The one-delayed clock in the clock is exclusive-ORed with the original input clock CK in the exclusive-OR circuit 2, and the clock CK2F with twice the frequency is output to the output terminal 4. generated.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the circuit configuration of an embodiment of the multiplier circuit according to the present invention, and FIGS. 3 and 4 show their time charts.

In FIG. 2, numerals 1, 2, 5, and 7 correspond to those in FIG. 1, and 3.4 corresponds to those in FIG. code 8
1 to 12 are flip-flop circuits, 13 is a decoder circuit, and 14 is a time constant circuit.

The delay circuit section l has a delay clock C extracted from an even number of inverters that is theoretically delayed by a phase A with respect to the period T of the input clock CK input to the input terminal 3.
KDb, a delayed clock CKDa extracted from the position a of the inverter two places before the delayed clock CKDb, and a position C of the inverter two places after the delayed clock CKDb.
The delayed clock CKDc extracted from the clock CKDc is output, and each of the delayed clocks CKDa, CKDb, and CKDc is input to the selector. Assuming that the operating time of each inverter constituting the delay circuit section l is the standard T, that is, the standard delay time of one inverter is T,
When closed, the delay clock CKDb is the input clock CK.
The number of inverters N is an integer equal to N-(To /4) x 1/Ts, and the delayed clock CKDb is output from an even numbered position so that the delay clock CKDb is delayed by the phase of A of the period To. It is configured.

The phase detection delay circuit section 5 has a period T of the input clock CK.
In order to obtain a phase detection delay clock that is delayed by one or more phases of 0, N+2 delay inverters are provided at the next stage of the delay circuit section 1.

FIG. 2 shows an example of N-6, and even number of inverter positions C2d, e, r in the phase detection delay circuit section 5 are shown.
, g, the phase detection delay clocks are extracted, respectively.
The signals are input to correspondingly provided flip-flop circuits 8 to 12, respectively. These flip-flop circuits 8 to 12 and the phase detection delay circuit section 5 detect a phase detection delay clock that exceeds the phase of the period A of the input clock CK.

The decoder circuit 13 outputs the delayed clock C from the delay circuit unit 1 input to the selector 7 according to the combination of signals output from the flip-flop circuits 8 to 12.
It outputs a selector control signal l for selecting which delayed clock among KDa, CKDb, and CKDC.

Further, the time constant circuit 14 is provided to suppress jitter of the doubled clock CK2F output from the exclusive OR circuit 2 due to a change in the selector control signal l output from the decoder circuit 13. .

The input clock CK of frequency f input to the input terminal 3 is propagated through the series-connected inverters in the delay circuit section 1. At this time, the even number of inverters are at positions a and b.
, C respectively extracted delayed clocks CKDa, C
KDb and CKDc are input to the selector 7.

When each inverter constituting the delay circuit section 1 operates at a standard operating time, the delay time of the delay clock CKDb is about a phase of the period T of the input clock CK, as shown in FIG. There is.

Further, at this time, the delay time of the phase detection delay clock extracted from the position e in the two-phase detection delay circuit section 5 is:
The period T of the input clock CK exceeds the phase A of the input clock CK, and as shown in FIG.
A signal of "@H" is output.Similarly, a signal of "H" is output from the flip-flop circuits 11.12, but a signal of 'L' is output from the flip-flop circuit 8.9. Each of these flip-flop circuits 8 to 12
The data of the combinations are decoded by the decoder circuit 13 and 9
The selector control signal 5 for selecting the delayed clock CKDb from the delay circuit unit 1 is sent to the selector 7 via the time constant circuit 14.
Output towards.

The delayed clock CKDb selected by the selector 7 is exclusive-ORed with the input clock CK by the exclusive-OR circuit 2, and is converted into a double clock C with a good duty as shown in FIG.
K2F is output to output terminal 4.

Note that the second time constant circuit 14 operates for phase detection and updates the select control signal only when the data of the flip-flop circuits 8 to 12 that operate for phase detection does not change for a certain period of time or more, and updates the select control signal 2 generated from the exclusive OR circuit 2. It operates to suppress jitter of the multiplied clock CK2F.

The time chart in FIG. 4 shows the time when the delay time of the delay circuit section 1 is the minimum.

At this time, the delay time of the phase detection delay clock extracted from the position g in the 9 phase detection delay circuit section 5 exceeds the phase A of the period T of the input clock CK, and the flip “H” from the flop circuit 12 as shown in FIG.
signal is output.

All other flip-flop circuits 8 to 11 are @L
The data of the combinations of these flip-flop circuits 8 to 12 are decoded by the decoder circuit 13 and sent through the time constant circuit 14 to select the delayed clock CKDc from the delay circuit section 1. Output signal i to the selector.

The delayed clock CKDc selected by the selector 7 is subjected to an exclusive OR operation with the input clock CK in the exclusive OR circuit 2, and is converted into a double clock C with a good ratio as shown in FIG.
K2F is output to output terminal 4.

Note that when the delay time of the delay circuit section 1 is slower than the standard delay time, the selector 7 is controlled to select the delayed clock CKDa, and the exclusive OR of the delayed clock CKDa and the original input clock CK is determined. Needless to say, the doubled clock GK2F with a good duty factor is output to the output terminal 4.

Inverters of the input/output inversion circuit are handled in units of two as delay elements of the delay circuit section 1 and the phase detection delay circuit section 5, but instead of the inverters in units of two, a buffer whose input and output are the same signal can be used. It can be used as a delay element. In this case, since the input and output are the same signal, unlike the case of an inverter, the delayed clock and phase detection delay clock can be extracted from any position.

[Effects of the Invention] As explained above, according to the present invention, it is possible to generate a double clock with good deity.

An integrated circuit that would otherwise malfunction due to variations in delay elements can be repaired. Furthermore, variations in the pulse width of the doubled signal can be suppressed to the width of two delay gate circuits.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of a multiplier circuit according to the present invention. FIG. 2 shows the circuit configuration of an embodiment of the transmitting circuit according to the present invention, FIGS. 3 and 4 show its time chart, FIG. 5 shows the conventional circuit structure, and FIG. 6 shows its time chart. In the figure, 1 is a delay circuit section, and 2 is an exclusive OR circuit. 5 is a delay circuit for phase detection, 6 is a phase detector, 7 is a selector, 8 to 12 are flip-flop circuits, 13 is a decoder circuit, and 14 is a time constant circuit.

Claims (1)

[Claims] Delay gate circuits are connected in series, an input clock is delayed using the operating time, and a clock with twice the frequency is generated from the delayed delay clock and the original input clock. In the multiplier circuit of an integrated circuit, when the delay gate circuit is assumed to operate in the standard operating time, the phase of the delay clock is 1/4 of the input clock.
A delay circuit unit (1) that outputs delayed clocks from the position of a delay gate circuit that causes a phase lag and the position of ±n gate circuits from this position, and a delay circuit unit (1) that outputs delayed clocks from the position of the delay gate circuit that causes a phase lag, and a delay circuit unit (1) that outputs delayed clocks from the position of the delay gate circuit that causes a phase lag, and the position of the gate circuit that is ±n from this position, and a delay circuit unit (1) that outputs delayed clocks from the position of the delay gate circuit that is phase delayed A phase detection delay circuit section (5) in which n gates are connected in units of n and outputs a phase detection clock at each connection position, and a phase detection delay circuit section (5) that outputs a phase detection clock at each connection position; A phase detection unit (6) detects a phase detection clock whose phase delay exceeds 1/2 phase of the input clock.
), and a selector () that selects the delayed clock of the delay circuit section (1) according to the extraction position of the phase detection delay circuit section (5) of the phase detection clock detected by the phase detection section (6). 7), and an exclusive OR circuit (2) that generates a clock with twice the frequency from the delayed clock selected by the selector (7) and the original input clock, so that the clock is generated within a predetermined threshold. A multiplication circuit characterized in that it accommodates variations in pulse width of a double multiplication clock.