JPH0619719B2 - Interrupt circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt circuit for supplying an interrupt signal to a microprocessor or the like.

[Conventional technology]

FIG. 3 shows an example of a conventional interrupt circuit.
0) to (14) and (31) are flip-flops (hereinafter referred to as F / F), (20) is an encoder with priority, (30) is a latch element, and (I ₀ ) to (I ₄ ) are Factor, (40) is the reference clock
CK is shown, and the interrupt circuit having the configuration operates as follows.

The operation of the illustrated configuration will be described with reference to FIG. Of the interrupt factors (I ₀ ) to (I ₄ ), for example, when the interrupt factor (I ₀ ) becomes active, the F / F (10) operates and the Low active signal changes to the above F / F ( It is output from 10) and input to the encoder with priority (20).

The encoder with priority (20) outputs a signal indicating that an interrupt has occurred and, at the same time, outputs an encoding result indicating which interrupt factor to the F / F (31) and the latch element (30). Therefore, the F / F (31) and the latch element (3
0) latches the interrupt generation signal and the encoding result based on the reference clock (40), and enables information to be provided to, for example, a microprocessor (not shown) in the system.

[Problems to be solved by the invention]

Since the conventional interrupt circuit is configured as above,
When the interrupt factors (I ₀ ) to (I ₄ ) are asynchronous with the reference clock (40), the interrupt factor (I ₀ ) occurs just before the reference clock (40) rises, as shown in FIG. 4, for example. In that case, the latch element (30) latches the encoding result in the transient state, which causes a malfunction. That is, the interrupt factor (I
( ₀ ) latches the encoding result (CBA) = (001) in F / F (30), but as a result, latches (CBA) = (001) and it is considered that the interrupt factor (I ₂ ) occurred. This may cause a malfunction.

The present invention has been made to solve the above problems, and an interrupt circuit that does not erroneously output a transient state as interrupt information even if an interrupt factor is input asynchronously with a reference clock. The purpose is to provide.

[Means for solving problems]

In the interrupt circuit according to the present invention, between the first flip-flop and the encoder, a knot element that inverts the reference clock and the latch output of the first flip-flop based on the inverted signal are latched, and The second flip-flop outputs to the encoder, and the synchronization means for synchronizing the output of the encoder and the latch operation of the latch element is provided.

[Action]

By the synchronizing means according to the present invention, the signal obtained by inverting the reference clock by the knot element is input to the second flip-flop, the interrupt factor from the first flip-flop is latched at the falling edge of the reference clock, and the reference clock is dropped. Input to the encoder at the timing synchronized with.

〔Example〕

FIG. 1 is a circuit diagram according to an embodiment of the present invention shown corresponding to a conventional example. In FIG. 1, the components designated by the same reference numerals as those in FIG. 2 have the same or similar functions. Therefore, (50) to (54) indicate the second plurality of flip-flops, (60) indicates the knot display, and the reference clock CK
(40) is a configuration obtained by inverting the signal via the knot element (60) as the clock of the flip-flops (50) to (54),
As a result, a synchronization means for synchronizing the encoder with priority (20) and the latch element (30) is formed.

Next, the operation will be described with reference to the timing chart of FIG. Of the interrupt factors (I ₀ ) to (I ₄ ), for example, when the interrupt factor (I ₀ ) becomes active, the F / F (10) operates and goes low.
An active signal is output and input to the data input terminal of the F / F (50) at the next stage.

However, since a signal obtained by inverting the reference clock (40) with the knot element (60) is input to the CK terminal of the F / F (50), the interrupt factor (I ₀ ) is the reference clock ( It will be latched at the falling edge of 40), and the latch output is input to the encoder with priority (20).

The encoder with priority (20) outputs a signal indicating that an interrupt has occurred, and at the same time outputs an encoding result indicating which interrupt factor has occurred, and outputs it to the F / F (31) and the latch element (30) respectively. input. Above F / F (31) and latch element (30)
Latches the interrupt generation signal and the encoding result at the reference clock (40), and makes it possible to provide information to, for example, a microprocessor (not shown) in the system. That is,
Since there is sufficient time for the F / F (30) to latch the data after the output of the encoder (20) changes, the problem as in the conventional example does not occur. Where the reference clock (40) is 50
The signal of% duty is assumed, and the encoding result is set to be sufficiently stable within the time of 1/2 × (reference clock cycle). Also, the time T is the delay time Td of the encoder (20) and the setup time Ts of the F / F (30).
On the other hand, if T> Td + Ts is satisfied, the clock signal to the F / Fs (50) to (54) does not have to be the inverted signal of the reference clock CK (40).

In this embodiment, the F / Fs (50) to (54) are described as being configured by individual F / Fs, but it goes without saying that the same effect can be obtained by configuring a plurality of built-in storage elements. Yes. Also, above F /
The CK input of F (50) to (54) was explained as the inverted signal of the reference clock (40), but the CK input of F / F (50) to (54) rises after the CK input of F / F (50) to (54) rises. Needless to say, the same effect can be obtained by using any clock other than the fall of the reference clock as long as the encoding result is sufficiently stable within the time until the rise of the input (reference clock). Further, although the present invention has been described with five types of interrupt factors, it is needless to say that the same effect can be obtained with more or less (two or more) factors.

〔The invention's effect〕

As described above, according to the present invention, the knot element that inverts the reference clock and the latch output of the first flip-flop based on the inverted signal are latched between the first flip-flop and the encoder. A synchronizing means including a second flip-flop for outputting to the encoder is provided, and an interrupt factor from the first flip-flop is latched at the falling edge of the reference clock, and the encoder is synchronized with the reference clock at a timing. Since the input is made, the interrupt factor can be output to the encoder at the timing synchronized with the reference clock without providing delay means or the like. Therefore, after the clock input of the second flip-flop rises, the clock input of the latch element rises. It is possible to stabilize the encoding result within the time until An effect that is.

[Brief description of drawings]

FIG. 1 is a configuration diagram according to an embodiment of the present invention, FIG. 2 is a time chart of each part of FIG. 1, FIG. 3 is a configuration diagram of a conventional example,
FIG. 4 is a time chart of each part of FIG. In the figure, (10) to (14) are flip-flops, (20) is an encoder with priority, (30) is a latch element, (31) is a flip-flop, (40) is a reference clock, and (50) to (51 ) Is a flip-flop, (I ₀ ) to (I ₄ ) are interrupt factors, and (60) is a knot element. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first latch for each of a plurality of interrupt factors.
Flip-flops, an encoder with priority that outputs an interrupt generation signal based on the latch outputs of these flip-flops, and an encoding result that indicates one of the above-mentioned interrupt factors, and a reference clock. In the interrupt circuit provided with a latch element that latches and outputs the interrupt generation signal and the encoding result based on
A knot element that inverts the reference clock between the first flip-flop and the encoder, and a second flip-flop that latches the latch output of the first flip-flop based on the inverted signal and outputs the latched output to the encoder. An interrupt circuit comprising: a flip-flop and a synchronization means for synchronizing the output of the encoder and the latch operation of the latch element.