JPH06101673B2 - Flip-flop circuit - Google Patents

Description

The present invention relates to a flip-flop circuit that holds and outputs given data in synchronism with a clock signal, and in particular, it is asynchronous with respect to the clock signal. The present invention relates to a flip-flop circuit suitable for processing input data.

(Prior Art) Conventionally used flip-flop circuits (hereinafter referred to as “F / F circuits”) include those shown in FIG. 3, for example.

FIG. 3 is a diagram showing the configuration of a latch type F / F circuit called a master-slave type.

In FIG. 3, the F / F circuit includes a clocked inverter whose master section and slave section operate as inverters in one state (for example, high level state) of the clock signal (CK) and the other of the clock signal (CK). In this state (for example, low level state), it is composed of a clocked inverter that operates as an inverter and a normal inverter.
In the master section and the slave section, the output terminal of the clocked inverter is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the input terminal of the clocked inverter to latch the given data.

In such a configuration, in the F / F circuit, as shown in FIG. 4, the master unit captures and holds the input data (D) in the first half of the clock signal CK (in the high level state), The slave unit takes in and holds the input data held by the master unit in the latter half of the clock signal CK (in the low level state). As a result, the F / F circuit holds the input data at the falling edge of the clock signal CK for one clock period.

In the latch circuit provided in such an F / F circuit,
When the inverter and the clocked inverter are operated with a power supply voltage of 5 V, for example, and the threshold voltages of both are 2.5 V, for example, a shown in FIG.
The potential of the point may stabilize at potentials of 2.5V other than 0V and 5V.

Such a state is called a metastable state as opposed to a stable state where the potential is 0 V or 5 V, but this metastable state is not a strong stable state, and it shifts to one stable state due to a disturbance such as slight noise. Resulting in.

The voltage that can be held in the metastable state of the latch circuit shown in FIG. 3 is a non-linear input / output characteristic of inverters cascaded in two stages with one input / output connection point of the latch circuit open. , The input voltage of the first-stage inverter is equal to the output voltage of the second-stage inverter, and the rate of change at that time is 1 or more. Such a voltage value depends on the size of the transistor that constitutes the inverter. It is decided as a matter of interest. Therefore, the voltage value that can be maintained in the metastable state is not limited to 2.5V.

When such a metastable state occurs in the circuit, the input level is not fixed in the circuit in the subsequent stage, and the input level is judged to be "0" or "1" depending on the electrical characteristics of the circuit itself. However, since the metastable state is not a strong stable state, a sudden transition from the metastable state to one stable state may cause a malfunction.

For example, as shown in FIG. 5, an arithmetic circuit A having a short arithmetic time and an arithmetic circuit B having a long arithmetic time receive the output Q of the F / F circuit 1 having the configuration shown in FIG. The
If the F / F circuit 1 suddenly shifts from the metastable state to the stable state when the same calculation result is stored in the corresponding registers A and B, the calculation of the calculation circuit B is slow,
This causes a problem that different contents are stored in the respective registers A and B.

(Problems to be Solved by the Invention) As described above, in the conventional static F / F circuit, when the metastable state transits to the stable state, a malfunction occurs in the subsequent circuit that receives the output of the F / F circuit. There was a problem that occurred. This is because the level of the input data is not fixed when trying to hold the input data.

Therefore, in the conventional static F / F circuit, the specifications are set so that the input data is fixed for a certain time before and after the rising or falling edge of the signal that captures the input data. Has been. However, in the synchronous system, when the input data given from the outside is asynchronous with respect to the clock signal, it becomes impossible for the input data to always satisfy the above specifications. Therefore, an F / F that receives input data that is asynchronous to the clock signal
In the circuit, the above-mentioned problems are caused.

To deal with such a problem, conventionally, by connecting a large number of F / F circuits in series and passing intermediate level input data through a large number of F / F circuits, the output level can be changed to "1" level or " It was fixed at 0 "level. However,
Such measures require a considerable amount of F / F circuits, which causes a problem that the configuration becomes large.

Therefore, the present invention has been made in view of the above, and an object thereof is to provide input data that is asynchronous with respect to a clock signal in a flip-flop circuit that holds a voltage corresponding to binary logic. However, a flip-flop circuit that stabilizes the output without increasing the size of the configuration may be provided.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention is a flip-flop circuit that holds binary logic, in which two states are synchronized with one state of a clock signal. A first logic value or a second logic value of the value logic is held, and the value logic is within a range between the voltage value corresponding to the first logic value and the voltage value corresponding to the second logic value. A holding circuit capable of holding a third voltage value other than the first or second voltage value, and 2 in synchronization with the other state of the clock signal.
Holds the first logical value or the second logical value in the value logic,
A holding circuit that holds a third voltage value other than the first or second voltage value within the range of the voltage value corresponding to the first logical value and the voltage value corresponding to the second logical value Alternate with 3
It is characterized in that they are connected in cascade in more than one stage, and the third voltage value of the holding circuit of the first stage and the third voltage value of the holding circuit of the next stage are different.

(Operation) In the above configuration, the present invention changes the third voltage value of the holding circuit of the first stage and the holding circuit of the next stage so that the holding circuit of the first stage holds the third voltage value in the metastable state. , The holding circuit at the next stage holds the first or second logical value in a stable state,
The output is made sure to be in the "0" level state or "1" level state.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

In the present invention, the metastable state is not generated conventionally, but it is unavoidable that the metastable state is generated in the latch circuit in the first stage, and measures are taken after the first stage. I have to.

FIG. 1 is a diagram showing the configuration of an F / F circuit according to an embodiment of the present invention.

In FIG. 1, the F / F circuit includes three stages of cascade-connected latch circuits 11, 13, and 15. Each latch circuit
11, 13, 15 are composed of an inverter and a clocked inverter.

In the latch circuits 11 and 15, the output end of the inverter is connected to the input end of a clocked inverter that operates as an inverter when the clock signal (CK) is in one state (for example, high level state), and the output end of the clocked inverter is It is configured to be connected to the input terminal of the inverter.

The latch circuit 13 has an output terminal of the inverter connected to an input terminal of a clocked inverter that operates as an inverter in the other state of the clock signal (CK) (for example, a low level state), and an output terminal of the clocked inverter is input to the inverter. It is configured to be connected to the end.

The latch circuit 11 is connected to the latch circuit 13 via a clocked inverter that operates as an inverter in one state of the clock signal (CK), and the latch circuit 13 operates as an inverter in the other state of the clock signal (CK). It is connected to the latch circuit 15 via a clocked inverter.

Input data (D) is given to the latch circuit 11 via a clocked inverter that operates as an inverter in the other state of the clock signal (CK), and the latch circuit 15
Is output to the subsequent stage as an output (Q) via an inverter connected in series in two stages.

The threshold voltage of the latch circuit 11 is set so that when the power supply potential is set to, for example, 5V, the points a and b in FIG. In the latch circuit 13, the point c in FIG. 1 is, for example, 2.8V.
The threshold voltage is set so that the point d in FIG.

Next, the operation of this embodiment will be described with reference to the timing chart shown in FIG.

Input data (D) at the rising edge of clock signal
Is about 2.5V, as shown in Fig. 2,
The input data of this voltage is taken into the latch circuit 11 and held by the latch circuit 11 while the clock signal CK is in the high level state. During this period, the output is held by the latch circuit 15, and the output of the F / F circuit is not affected by the circuit 11 holding a voltage of about 2.5V. This makes the first
The potential at point b in the figure becomes a voltage of about 2.5 V as shown in FIG.
Given to 13.

The latch circuit 13 receives input data with a voltage of about 2.5V, but since the voltages at the metastable state at points c and d in FIG. 1 are set to 2.8V, 2 and 3V, respectively, the latch circuit 13 13 does not become a metastable state, and the voltage at point d is 2. as shown in Fig. 2.
It is higher than the voltage of about 5V.

In such a state, when the clock signal changes from the high level state to the low level state, the latch circuit 13 causes the latch circuit 11 to
And electrically separated. As a result, the voltage at point d in FIG. 1 rises to the power supply potential of 5 V as shown in FIG. Therefore, the latch circuit 15 captures and holds the output of the latch circuit 13 that has reached 5 V, and reliably holds it in a high level state.
Provides an output Q of 5V.

As described above, in this embodiment, even if the latch circuit 11 in the first stage is in the metastable state, the latch circuit 13 in the next stage is set in the stable state, so that the output can be stabilized in a reliable high level state. it can.

In the above embodiment, the voltage held in the metastable state is not limited to 2.5V as described in the section of the related art, and is set as a circuit design item as a voltage value between both power supply voltages. , Irrespective of the voltage value held as the metastable state in the first stage, the voltage value held as the metastable state of the latch circuit in the next stage is set to be different from the voltage value held as the set metastable state. If set, it is possible to obtain the same operational effect as described above.

[Effects of the Invention] As described above, according to the present invention, even if the holding circuit in the first stage is in the metastable state, the holding circuit in the next stage is in the stable state. Further, by making the number of holding circuits three or more, the influence of the metastable state of the holding circuit in the first stage does not appear on the external output, so that even if the input data is asynchronous with respect to the clock signal, the output can be reliably output. "0"
The output can be stabilized in the level state or "1" level state.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of a flip-flop circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of the flip-flop circuit shown in FIG. 1, and FIG. 3 is a conventional static flip-flop circuit. Figure showing the configuration, fourth
FIG. 5 is a timing chart of the flip-flop circuit shown in FIG. 3, and FIG. 5 is a diagram showing a circuit configuration using the flip-flop circuit shown in FIG. 11,13,15 …… Latch circuit

Claims (1)

[Claims] 1. A flip-flop circuit holding binary logic, which holds a first logical value or a second logical value among binary logic in synchronization with one state of a clock signal, and A holding circuit capable of holding a third voltage value other than the first or second voltage value within a range of a voltage value corresponding to the first logical value and a voltage value corresponding to the second logical value; , A first logic value or a second logic value of the binary logic is held in synchronization with the other state of the clock signal, and a voltage value and a second logic value corresponding to the first logic value are held. A holding circuit capable of holding a third voltage value other than the first or second voltage value within a range of the corresponding voltage value is alternately cascaded in three or more stages, and the third holding circuit of the first stage is connected. Voltage value and the third holding circuit of the next stage
The flip-flop circuit is characterized in that it is different from the voltage value of.