KR19990048767A - Gated Clock Circuit with Glitch Rejection - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gated clock circuit that combines and outputs an input signal and a clock signal. The present invention relates to a first clock outputting the input signal in synchronization with an inverted clock signal. A flip flop 41; A second flip flop (42) for outputting an output signal (A) of the first flip flop (41) in synchronization with a clock signal (CLK); And a logic circuit 43 for logically calculating and outputting the output signal A of the first flip flop 41 and the output signal B of the second flip flop 42. When the clock signal is input, glitches that may be generated are removed to output a normal output signal.

Description

GATED CLOCK CIRCUIT WITH GLITCH ELIMINATING FUNCTION

The present invention relates to a gated clock circuit for combining and outputting an input signal and a clock signal.

In designing a circuit, an output signal may be generated by directly combining an input signal and a clock signal to produce a desired output signal. Such a circuit is called a gated clock circuit. In this case, the signal generated by the gated clock circuit changes the pulse characteristic of the clock signal in response to a change in temperature or a frequency, thereby generating glitches due to an instantaneous abnormality of current. Output signals containing glitches caused by any cause can cause fatal malfunctions when input to subtle circuits such as counters.

1 is a circuit diagram of a conventional gated clock circuit, Figure 2 is a timing diagram for the operation of the gated clock circuit shown in Figure 1, Figure 3 is a high frequency clock in the gated clock circuit shown in FIG. This is a timing chart showing when glitches occur in the output signal when operated.

The gated clock circuit as shown in FIG. 1 is comprised of a flip flop 11 and a NAND gate 12. The flip flop 11 outputs an input signal Input to the NAND gate 12 in synchronization with the inverted clock signal CLKb. The NAND gate 12 combines a clock signal CLK and an output A of the flip flop 11 to output an output signal. The normal operation of the conventional gated clock circuit as described above is as shown in FIG. However, when the clock signal is input twice as fast as the case shown in FIG. 2, the cleat 31 is generated in the output signal Output as shown in FIG. 3.

That is, as shown in FIG. 2, when the clock signal CLK has a low frequency, no glitch occurs in the output signal. However, when the temperature rise or the clock signal CLK having a faster frequency is input, there is a possibility that glitches occur in the output signal Output. In the case illustrated in FIG. 3, glitches are generated in the output signal Output when the clock signal CLK has a frequency twice as fast as the clock signal CLK of FIG. 2. The occurrence of these glitches has a fatal effect on the circuit receiving the output signal (Output).

Accordingly, an object of the present invention is to provide a gated clock circuit having a glitch cancellation function as proposed to solve the above-mentioned problems.

1 is a circuit diagram of a conventional gated clock circuit;

2 is a timing diagram for the operation of the gated clock circuit shown in FIG.

3 is a timing diagram showing a case where glitches occur in an output signal when operated with a high frequency clock in the gated clock circuit shown in FIG. 1;

4 is a detailed circuit diagram of a gated clock circuit with glitch cancellation in accordance with an embodiment of the present invention; And

5 and 6 are timing diagrams illustrating an operation of a gated clock circuit having a glitch cancellation function illustrated in FIG. 4.

* Description of the symbols for the main parts of the drawings *

11, 41, 42: flip flop 12: logic circuit

31: Glitch

According to a feature of the present invention for achieving the above object of the present invention, there is provided a gated clock circuit having a glitch cancellation function: a first flip-flop for outputting an input signal in synchronization with an inverted clock signal; A second flip flop for outputting an output signal of the first flip flop in synchronization with a clock signal; And a logic circuit for performing a logic operation on the output signal of the first flip flop and the output signal of the second flip flop to remove glitches that may occur when a temperature change or a high frequency clock signal is input.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The gated clock circuit having the novel glitch elimination function of the present invention generates an output signal using flip-flops to eliminate the problem of glitch as in the prior art, thereby eliminating glitch and desired You can create an output signal.

4 is a detailed circuit diagram of a gated clock circuit having a glitch cancellation function according to an embodiment of the present invention, and FIGS. 5 and 6 are views illustrating an operation of a gated clock circuit having a glitch cancellation function shown in FIG. 4. The following is a timing chart.

As shown in FIG. 4, the gated clock circuit according to the embodiment of the present invention includes a first flip flop 41, a second flip flop 42, and a NAND gate 43. The first flip flop 41 outputs the input signal Input in synchronization with the inverted clock signal CLKb. The second flip flop 42 receives the output signal A of the first flip flop 41 and outputs the same in synchronization with the clock signal CLK. The output signal B of the second flip flop 42 and the output signal A of the first flip flop 41 are input to the NAMD gate 43, and finally an output signal Output is output. The gated clock circuit having the glitch removal function as described above removes the glitch by using the second flip flop 42. Of course, unlike the related art, one more flip flop is used, but the entire circuit generates an output signal very stably in operation.

5 and 6 show operation characteristics of the gated clock circuit having the glitch elimination function described above. FIG. 5 illustrates a case in which the frequency is the same as that shown in FIG. 6 illustrates a case where a clock signal having a high frequency of twice as fast as the clock signal shown in FIG. 5 is input as shown in FIG. 3. As shown in FIG. 6, even when a high frequency clock signal CLK is input, an output signal Output is normally output without generating glitches as in the prior art.

According to the present invention as described above, it is possible to stably generate the thrust signal by removing the glitches that can occur when using a change in the ambient temperature or a high frequency clock signal as conventionally.

Claims (1)

For gated clock circuits: A first flip flop 41 which outputs an input signal in synchronization with an inverted clock signal; A second flip flop (42) for outputting an output signal (A) of the first flip flop (41) in synchronization with a clock signal (CLK); And a logic circuit 43 for performing a logic operation on the output signal A of the first flip flop 41 and the output signal B of the second flip flop 42, 2. A gated clock circuit having a glitch removal function, which eliminates glitches that may occur when a temperature change or a high frequency clock signal is input.