JPS6022542B2 - synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization circuit, and particularly to a high-speed synchronization circuit with a noise removal function.

In electronic computers or communication devices, it is usually necessary to synchronize the reception of signals from external devices with internal processing cycles.

For this reason, a circuit is provided for synchronizing asynchronous signals and removing uncertain noise caused by an abnormality in an external device or generated in a transmission path. Along with noise, all narrow signals that cannot mimic the normal waveform are removed, and only signals longer than the cycle period are latched as valid inputs. FIG. 1 is a block diagram showing an example of a conventional synchronization circuit with noise removal function, and FIG. 2 is an operation time chart of FIG. 1.
In the figure, four latches 2, 4, 6, and 10 are arranged in series, and the output of the final stage flip-flop 10 is shaped, ignoring noise with a pulse width within 2 cycles. , giving a synchronized signal.

First, when the AND outputs of timings T1 and GT shown in FIG. 2b and c are used as clock inputs, and the signal input shown in FIG. 2e is set in the D-type flip-flop 2, the output shown in FIG. This becomes the data input for flip-flop 4.

Since the flip-flop 4 uses the AND output of the timing TO shown in FIG. 2a and the inverted number of the timing HT shown in FIG. 2a as a clock input, the flip-flop 2 It is set 1.5 cycles later than the output of .

Flip-flop 6 uses the output of flip-flop 4 as data input, and uses timing TI and timing GT as data input.
Since the AND output of the inverted signal of is used as the clock input, it is set 1.5 cycles later than the output of the flip-flop 4, as shown in FIG. 2h.

The final stage flip-flop 10', well, flip.

It is set by the AND output of the output of flip-flop 2, the output of flip-flop 6, and the inverted signals of timing To and HT.
It is reset by the AND output of the inverted signal of (see FIG. 2i). In this way, "In the circuit shown in FIG. 1, the set time difference between the first and second stage flip-flops and between the second and third stage flip-flops is 1.5 cycles. This period is "It must be longer than the uncertainty time of the output when the asynchronous signal is latched. Also, since the first stage flip-flop 2 is set once every two cycles, the first stage flip-flop - The change in flop 2 may occur at most 2 cycles before the actual input signal XI.In other words, from the signal change in input signal XI to the output change in flip-flop 10 at the final stage, there is a maximum of 5.5
It will take a cycle. This is too slow for a device that must respond quickly to the input signal XI. The purpose of the present invention is to eliminate the noise generated in the transmission path and minimize the delay caused by waiting for the uncertain time caused by synchronization, in order to eliminate the conventional drawbacks.
An object of the present invention is to provide a synchronization circuit that achieves both high speed and noise removal function.

The synchronization circuit of the present invention can virtually set the input signal every cycle by arranging flip-flops in parallel that are set once every two cycles and setting them alternately with a one-cycle difference. In order to wait for the uncertainty period of 1.5 cycles, connect one more stage flip-flop to each in series, match their outputs, and absorb noise within one cycle. It is a feature.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of the synchronization circuit of the present invention, and FIG. 4 is an operation timing chart of FIG.

The timings To and T are 1' as shown in FIG. 4a.
It has a phase difference of 2 cycles.

Flip-flops 11 and 12 use these timings To, T, to generate two timings GT and HT shown in FIG. 4b. In this case, the input data of the flip-flop 11 is the "0" side output of the flip-flop 12, while the input data of the flip-flop 12 is the "1" side output of the flip-flop 11.

Flip flop. When the pins 11 and 12 are set to "0" and "1", oscillation signals GT and HT having a pulse width of one cycle are obtained at twice the cycle period compared to the timings To and T. Timing GT precedes HT by 1/2 cycle. Flip-flops 15 and 16 receive the asynchronous signal XI as input data, and each has a timing GT of "0".
” and when it is “1”, the AND output with timing T becomes “1” and is set.

Each output signal XI of the next flip-flop 15, 16
A0, XIAI are flip-flop 19,
20 data input, and when the outputs of AND gates 17 and 18 become ``1'', flip-flops 19 and 2
Set to 0.

That is, when timing HT is “1” and “0”
”, the AND output at the timing becomes “1”, and its value is set 1.5 cycles later than the flip-flops 15 and 16 in the previous stage, as shown in FIG. Those two flip-flops 19, 20
When the outputs Xmo and X field 1 both become ``1'', the flip-flop 2 is
3 is set.

That is, when all the inputs of the AND gate 21 become "1", the flip-flop 23 is set, and the set output shown at X in FIG. 4c is obtained. Also,
Both flip-flops 19 and 20 are ``0''
When this occurs, flip-flop 23 is reset.
Thus, in FIG. 3, the asynchronous signal XI is input to the two flip-flops 15, 16, which are always set in alternating cycles, and the two flip-flops 15, 16 are always set in alternating cycles. Flip.

It is set in flops 19 and 20 after 1.5 cycles, respectively. And the rear flip-flop 19,2
When both are set to 0, the flip-flop 23 is set in response to the value, and the output of the flip-flop 23 is used for synchronization and for eliminating noise within one cycle (bipolar noise of tens and ones). It becomes a signal. In order for the asynchronous input signal XI to become the output value of this circuit, two parallel flips are required.

Both flops 15 and 16 must change.
In other words, if one is set to "1" but the other is not, input signals with a pulse width at the end of one cycle are removed, and only input signals with a pulse width of one cycle or more are considered normal signals. It is regarded. As explained above, according to the present invention, it is possible to effectively remove noise that is mixed in the transmission path or caused by a failure of an external device, and to minimize the delay due to waiting for an uncertain period. This is extremely effective when the period during which the output of the flip-flop is uncertain is longer than the cycle period.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional synchronization circuit, FIG. 2 is an operation time chart of FIG. 1, FIG. 3 is a block diagram of a synchronization circuit showing an embodiment of the present invention, and FIG. is the third
3 is an operation time chart of the figure.・'3, 5, 7, 8, 9, 13, 14 days 7, 18, 2
1, 22: And. Gate “2, 4, 6, 11, 12, 15, 16, 19,
20: D type flip-flop, 10, 23: SR type flip-flop, To, T,, GT, HT: timing signal, XI: asynchronous input signal. Figure 1 Figure N: Vertical dimensions of the Swallow map

Claims (1)

[Claims] 1 In a synchronization circuit that receives an asynchronous signal from the outside, removes noise, and synchronizes it with the internal clock, two clocks with a phase difference of 0.5 cycles are converted into two double cycles with a phase difference of 0.5 cycles. a circuit that generates a signal;
First and second flip-flops arranged in parallel are configured to take the asynchronous signal as input data and alternately set one of the clocks T1 as a clock depending on when one of the double period signals has a value of 0 or 1. Then, using the output signals of the first and second flip-flops as input data, the other one of the double period signals has a value of 0 or 1 so as to output an output signal delayed by 1.5 cycles from the flip-flop in the previous stage. The third and fourth flip-flops arranged in parallel alternately set the other one of the clocks T0 as the clock, and the clock T1 is set only when the values of the third and fourth flip-flops match. and a fifth flip-flop for setting the value by a synchronizing signal and outputting a synchronizing signal for the asynchronous signal.