KR100418572B1 - Asynchronous counting circuit - Google Patents

Abstract

The asynchronous counter circuit of the present invention provides a asynchronous counter circuit that prevents deviation of operation due to asynchronous between the CPU clock and the external clock by applying a digital logic structure that counts the asynchronous external count clock stably. There is this.

In order to achieve the above object, the present invention receives an internal synchronization clock signal and an internal clock signal, and receives a counter clock signal to generate a first reset signal, a second reset signal, a counter register set signal, and a counter register clear signal. Counting control means; A CPU which generates and outputs an internal synchronous clock signal, outputs an internal synchronous clock signal and an internal clock signal to the counting control means, and receives a carry value; And receiving an external clock signal and the internal synchronous clock signal from the CPU to generate the counter clock signal, output the counter clock signal to the counting control means, and receive the first reset signal. Counting means for performing a count according to the counter clock signal and outputs the count value, and counting means for outputting the carry value generated in the counting process to the CPU.

Description

Asynchronous Counter Circuit {ASYNCHRONOUS COUNTING CIRCUIT}

The present invention relates to an asynchronous counter circuit, and more particularly, to an asynchronous counter circuit used as a peripheral device of a microcontroller unit (MCU) to count an external clock that is not synchronized with an internal clock.

In general, the counter circuit counts the number of input pulses, which are counted by flip-flops being used as components and shifting in synchronism with clock pulses by cascading as necessary bits.

1 is a diagram illustrating a conventional asynchronous counter circuit, which receives an external clock signal through a clock terminal, loads and stores a new count value at each positive edge of the external clock signal, and increments the new count value. A count value storage register flip-flop 110 and a count value storage register flip-flop 110 outputted to the branch and the outside are input to the count value storage register flip-flop 110 by adding 1 to the count value. And an incrementer 120 outputting a carry value to the outside when a carry occurs.

In the conventional asynchronous counter circuit described above, since an external clock that is not synchronized with the CPU clock, which is an internal clock of the MCU, is used as an input pulse, there is a problem that the asynchronousness between the CPU clock and the external clock destabilizes the operation of the counter circuit. have.

SUMMARY OF THE INVENTION The present invention devised to solve the above problems provides a asynchronous counter circuit that prevents deviation of operation due to asynchronous between the CPU clock and the external clock by applying a digital logic structure that counts the asynchronous external count clock stably. Its purpose is to.

1 is an exemplary view showing a conventional asynchronous counter circuit,

2 is a block diagram illustrating an asynchronous counter circuit according to an embodiment of the present invention;

3 is an exemplary view showing counting means mounted in an asynchronous counter circuit according to an embodiment of the present invention;

4 is an exemplary view showing counting control means mounted in an asynchronous counter circuit according to an embodiment of the present invention;

5 is an operation timing diagram of an asynchronous counter circuit according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

210: counting control means

220: CPU

230: counting means

In order to achieve the above object, the asynchronous counter circuit of the present invention receives an internal synchronous clock signal and an internal clock signal, receives a counter clock signal, and clears a first reset signal, a second reset signal, a counter register set signal, and a counter register. Counting control means for generating a signal; A CPU which generates and outputs an internal synchronous clock signal, outputs an internal synchronous clock signal and an internal clock signal to the counting control means, and receives a carry value; And receiving an external clock signal and the internal synchronous clock signal from the CPU to generate the counter clock signal, output the counter clock signal to the counting control means, and receive the first reset signal. Counting means for performing a count according to the counter clock signal and outputs the count value, and counting means for outputting the carry value generated in the counting process to the CPU.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

First, Figure 2 is a block diagram showing an asynchronous counter circuit according to an embodiment of the present invention, the asynchronous counter circuit of the present invention includes a counting control means 210, a CPU 220 and counting means 230.

The counting control unit 210 receives the internal synchronous clock signal T5_ENB and the internal clock signal IPHI1 from the CPU 220, which will be described later, and receives the counter clock signal count_clk from the counting means 230, which will be described later. An internal synchronous clock control signal T5_ENB_pulse and a first flip-flop control signal CLR_FLAGS are generated, and a counter register set signal set_creg_b [15: 0] and a counter register clear signal are generated by the internal synchronous clock control signal T5_ENB_pulse. Counting means 230 generates (clear_creg_b [15: 0]) and outputs the counting means 230 to be described later, and generates the first reset signal rst_flag1 by the first flip-flop control signal CLR_FLAGS. Serves as.

In addition, the CPU 220 generates an internal synchronous clock signal T5_ENB and outputs it to the counting means 230 to be described later, and outputs the internal synchronous clock signal T5_ENB and the internal clock signal IPHI1 to the counting control means 210. And outputs the final carry value carry16 from the counting means 230 to be described later.

The counting means 230 receives an external clock signal count_clk_ext and the internal synchronous clock signal T5_ENB from the CPU 220, and generates the counter clock signal count_clk through the counter clock signal count_clk_ext and the counter clock. Outputs a signal count_clk to the counting control means 210, receives a first reset signal rst_flag1 from the counting control means 210, performs a count according to the counter clock signal count_clk, and counts the count. A value GREG [15: 0] is output, and a carry value carry16 generated in the counting process is output to the CPU 220.

3 is an exemplary view showing a counting means 230 mounted in an asynchronous counter circuit according to an embodiment of the present invention. The counting means 230 of the present invention includes a first AND gate 310 and a coefficient value storage register. A flip-flop 320, an incrementer 330, a temporary carry flip-flop 340, and a carry flip-flop 350.

The first AND gate 310 receives the external clock signal count_clk_ext from the outside, receives the internal synchronization clock signal T5_ENB from the CPU 220, performs an AND operation, and outputs the result value. Outputs to the counting control means 210, the coefficient value storage register flip-flop 320, the temporary carry flip-flop 340 to be described later, and the carry flip-flop 350 to be described later as a counter clock signal count_clk. Do it.

In addition, the coefficient value storage register flip-flop 320 receives the counter clock signal count_clk as a clock terminal and loads and stores a new coefficient value at each positive edge of the counter clock signal count_clk. The new count value is output to an incrementer 330 to be described later, and the counter register set signal set_creg_b [15: 0] and the counter register clear signal clear_creg_b [15: 0] are output from the counting control unit 210. It takes the input and performs the initialization process.

Meanwhile, the incrementer 330 receives a count value from the count storage register flip-flop 320, adds 1 to the count value, outputs the count value to the count storage register flip-flop 320, and a carry occurs. The carry value carry16_tmp is output to the temporary carry flip-flop 340 which will be described later.

In addition, the temporary carry flip-flop 340 receives an inverted value of the counter clock signal count_clk output from the first AND gate 310 as a clock terminal, and has a negative edge of the counter clock signal count_clk. Load the carry value (carry16_tmp) output from the integrator 330 according to the negative edge, output the carry value (carry16_tmp) to the carry flip-flop 350 to be described later as a temporary carry value (carry16_t) In this case, an initialization process is performed through the first reset signal rst_flag1 received from the counting control unit 210.

Meanwhile, the carry flip-flop 350 receives a value of the counter clock signal count_clk output from the first AND gate 310 as a clock terminal, and has a positive edge of the counter clock signal count_clk. In response to the temporary carry value (carry16_t) output from the temporary carry flip-flop 340, the temporary carry value (carry16_t) as the final carry value (carry16) to output to the CPU 220, the counting The initialization process is performed through the first reset signal rst_flag1 received from the control means 210.

4 is an exemplary view showing a counting control means 210 mounted in an asynchronous counter circuit according to an embodiment of the present invention. The counting control means 210 of the present invention is a first flip-flop control signal generating means 410. And an internal synchronous clock control signal generating means (420).

The first flip-flop control signal generating unit 410 receives an internal synchronous clock signal T5_ENB and an internal clock signal IPHI1 from the CPU 220, and thus, the second flip-flop control unit 410 and the third flip-flop control unit 410 will be described later. Generates a first flip-flop control signal CLR_FLAGS for performing initialization control of the flip-flop 422. In this case, the first flip-flop control signal generating means 410 includes a first flip-flop 411, an inverter 412, a first XOR gate 413, and a second AND gate 414.

The first flip-flop 411 mounted in the first flip-flop control signal generating means 410 receives an internal synchronous clock signal T5_ENB from the CPU 220 and an internal clock from the CPU 220. The internal synchronization clock signal T5_ENB is loaded according to the clock pulse of the signal IPHI1 and output to the first XOR gate 413 to be described later.

In addition, the inverter 412 mounted in the first flip-flop control signal generating means 410 receives an internal synchronous clock signal T5_ENB from the CPU 220 and inverts the value thereof to form a second AND gate (described later). 414).

Meanwhile, the first XOR gate 413 mounted in the first flip-flop control signal generating means 410 is a signal from the first flip-flop 411 and an internal synchronous clock signal T5_ENB from the CPU 220. After receiving the XOR operation and outputs the result to the second AND gate 414 to be described later.

In addition, the second AND gate 414 mounted in the first flip-flop control signal generator 410 receives a signal output from the inverter 412 and a signal output from the first XOR gate 413. And performs an AND operation, and outputs the result value as the first flip-flop control signal CLR_FLAGS.

Meanwhile, the internal synchronous clock control signal generating means 420 receives an internal synchronous clock signal T5_ENB from the CPU 220, receives the counter clock signal count_clk from the counting means 230, and An internal synchronous clock control signal T5_ENB_pulse is generated through the synchronous clock signal T5_ENB and the counter clock signal count_clk, and is initialized by receiving the second reset signal rst_flag2 by the first flip-flop control signal CLR_FLAGS. It plays a role. The internal synchronous clock control signal generating means 420 includes a second flip-flop 421, a third flip-flop 422, a second XOR gate 423, and a third AND gate 424.

The second flip-flop 421 mounted in the internal synchronous clock control signal generating means 420 receives an internal synchronous clock signal T5_ENB from the CPU 220 and receives the internal synchronous clock signal T5_ENB. The third flip-flop 422, the second XOR gate 423, and the third AND gate 424, which are loaded according to the positive edge of the counter clock signal count_clk received from the counting means 230, are described later. And a second reset signal rst_flag2 received by the first flip-flop control signal CLR_FLAGS to perform an initialization process.

In addition, the third flip-flop 422 mounted in the internal synchronous clock control signal generating means 420 receives a signal output from the second flip-flop 421 and receives the signal from the counting means 230. Loaded in accordance with the negative edge of the inverted counter clock signal count_clk received from the output, and outputs it to the second XOR gate 423 to be described later, the second reset by the first flip-flop control signal (CLR_FLAGS) It receives a signal rst_flag2 and performs an initialization process.

On the other hand, the second XOR gate 423 mounted in the internal synchronous clock control signal generating means 420 is a signal output from the second flip-flop 421 and a signal output from the third flip-flop 422. After receiving the XOR operation and outputs the result to the third AND gate 424 to be described later.

The third AND gate 424 mounted in the internal synchronous clock control signal generating means 420 may be a signal output from the second flip-flop 421 and a signal output from the second XOR gate 423. After inputting and performing an AND operation, the result is output as the internal synchronization clock control signal T5_ENB_pulse.

5 is an operation timing diagram of an asynchronous counter circuit according to an embodiment of the present invention. Operation of the asynchronous counter circuit of the present invention will be described below with reference to FIGS. 2, 3, 4, and 5.

In FIG. 3, the external clock signal count_clk_ext is an external asynchronous counting clock, and the internal synchronous clock signal T5_ENB is a signal for enabling a counter function and is a signal synchronized with the clock of the CPU 220.

First, when the internal synchronization clock signal T5_ENB becomes a high signal, the counter circuit is enabled. That is, the internal synchronous clock signal T5_ENB becomes the counter clock signal count_clk through the first AND gate 310, and the counter clock signal count_clk is the coefficient value storage register flip-flop that stores a count value. Acts as an enable clock signal. Afterwards, the value stored in the coefficient storage register flip-flop 320 is increased by 1 by the incrementer 330 to match the positive edge of the counter clock signal count_clk 320. ), The count value increases by one for each positive edge of the counter clock signal count_clk.

In addition, if the count value increases by 1 and the carry occurs, the generated carry value carry16_tmp may be adjusted to match the negative edge and the positive edge of the counter clock signal count_clk, respectively. In operation 350, the final carry value signal carry16 indicating that the overflow occurs to the CPU 220 is output.

At this time, the count value storage register flip-flop 320 may output the counter register set signal set_creg_b [15: 0] and the counter register clear signal clear_creg_b [15: 0] output from the counting control unit 210. When received, it is initialized to a predetermined value. In addition, the temporary carry flip-flop 340 and the carry flip-flop 350 perform an initialization process when the counting control means 210 receives the first reset signal rst_flag1. This clears the state of the previous counter circuit so that the previous value has no effect when the counter circuit is enabled again.

In addition, when an internal synchronization clock signal T5_ENB is input to the second flip-flop 421, the second flip-flop 421 is connected to the internal synchronization clock signal T5_ENB on a positive edge of the counter clock signal count_clk. ), And the third flip-flop 422 samples the internal synchronization clock signal T5_ENB on the negative edge of the counter clock signal count_clk. Afterwards, the operation is performed on the second XOR gate 423 and the third AND gate 424 using two sampled signals, thereby causing an internal synchronous clock to become high while the counter clock signal count_clk is high. The control signal T5_ENB_pulse is generated.

Thereafter, the counting control means 210 generates a counter register set signal set_creg_b [15: 0] and a counter register clear signal clear_creg_b [15: 0] through the internal synchronization clock control signal T5_ENB_pulse. These signals are input to the coefficient storage register flip-flop 320 to control the initialization process when the counter circuit is enabled / disabled by the internal synchronous clock signal T5_ENB.

In addition, when the internal synchronization clock signal T5_ENB becomes a low signal, the first flip-flop control signal generating means 410 during an interval in which the internal clock signal IPHI1, which is a CPU clock signal, is a low signal. Is activated to generate the first flip-flop control signal CLR_FLAGS. Thereafter, the counting control unit 210 generates a second reset signal rst_flag2 through the first flip-flop control signal CLR_FLAGS, and the second flip-flop 421 and the third flip-flop 422. Receives the second reset signal rst_flag2 and performs an initialization process. That is, an error occurs in generating the internal synchronization clock control signal T5_ENB_pulse by removing values remaining in the second flip-flop 421 and the third flip-flop 422 when the counter circuit is enabled through this initialization process. Do not have

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and the foregoing embodiments and the accompanying drawings. It is not limited to.

The present invention has the advantage of solving the problem that the operation of the counter circuit becomes unstable due to the asynchronous between the CPU clock and the external clock by applying a digital logic structure for stably counting the asynchronous external count clock.

Claims (5)

Counting control means for receiving an internal synchronous clock signal and an internal clock signal and receiving a counter clock signal to generate a first reset signal, a second reset signal, a counter register set signal, and a counter register clear signal; A CPU which generates and outputs an internal synchronous clock signal, outputs an internal synchronous clock signal and an internal clock signal to the counting control means, and receives a carry value; And Receives the external clock signal and the internal synchronous clock signal from the CPU to generate the counter clock signal, outputs the counter clock signal to the counting control means, receives the first reset signal, and receives the counter Counting means for performing a count according to a clock signal and outputting the count value, and outputting a carry value generated in the counting process to the CPU. Asynchronous counter circuit comprising a. The method of claim 1, wherein the counting means, A first AND gate receiving an external clock signal from an external device, performing an AND operation by receiving the internal synchronization clock signal from the CPU, and outputting the result as a counter clock signal to the counting control means; Receiving the counter clock signal through a clock terminal, loading and storing a new coefficient value at each positive edge of the counter clock signal, and receiving a counter register set signal and a counter register clear signal from the counting control unit to perform an initialization process Count value storage register flip-flop; An incrementer configured to receive a coefficient value from the coefficient storage register flip-flop, add 1 to the coefficient value, output the coefficient value storage register flip-flop, and output a carry value when a carry occurs; The inverted value of the counter clock signal output from the first AND gate is input to a clock terminal, and a carry value output from the incrementer is loaded according to a negative edge of the counter clock signal, and the carry value is temporarily stored. A temporary carry flip-flop that is output as a carry value and performs an initialization process through a first reset signal received from the counting control means; And The value of the counter clock signal output from the first AND gate is input to a clock terminal, and a temporary carry value output from the temporary carry flip-flop is loaded according to a positive edge of the counter clock signal, and the temporary carry value Is a final carry value and is output to the CPU, and a carry flip-flop that performs an initialization process through a first reset signal received from the counting control means. Asynchronous counter circuit comprising a. The method of claim 1 or 2, wherein the counting control means, First flip-flop control signal generation means for receiving an internal synchronization clock signal and an internal clock signal from the CPU and generating a first flip-flop control signal through the counting means; And Receiving an internal synchronous clock signal from the CPU, receiving the counter clock signal from the counting means, generating an internal synchronous clock control signal through the synchronous clock signal and the counter clock signal, and outputting it to the counting means, An internal synchronous clock control signal generating means for receiving the second reset signal and performing an initialization process Asynchronous counter circuit comprising a. The method of claim 3, wherein the first flip-flop control signal generating means, A first flip-flop that receives an internal synchronization clock signal from the CPU, and loads and outputs the internal synchronization clock signal according to a clock pulse of the internal clock signal from the CPU; An inverter which receives an internal synchronous clock signal from the CPU and inverts and outputs an internal synchronous clock signal; A first XOR gate receiving an input signal from the first flip-flop and an internal synchronization clock signal from the CPU, performing an XOR operation, and outputting a result value; And A second AND gate receiving the signal output from the inverter and the signal output from the first XOR gate, performing an AND operation, and outputting the result as the first flip-flop control signal to the counting means; Asynchronous counter circuit comprising a. The method of claim 3, wherein the internal synchronous clock control signal generating means, Receives an internal synchronization clock signal from the CPU, loads the internal synchronization clock signal according to a positive edge of the counter clock signal received from the counting means, and outputs the same; and performs an initialization process by receiving the second reset signal A second flip-flop; The signal output from the second flip-flop is input, the signal is loaded and output according to the negative edge of the inverted counter clock signal received from the counting means, and the initialization process is received by receiving the second reset signal. Performing a third flip-flop; A second XOR gate receiving an output signal from the second flip-flop and a signal output from the third flip-flop, performing an XOR operation, and outputting a result value; And A third AND gate which receives an output signal from the second flip-flop and a signal output from the second XOR gate, performs an AND operation, and outputs the result as an internal synchronous clock control signal; Asynchronous counter circuit comprising a.