KR19980065271A - Asynchronous counter circuit - Google Patents

Abstract

The present invention relates to an asynchronous counter circuit, comprising: counter means for generating at least two bits of binary coefficient output signals in response to an external clock, the counter means having at least two D-flip flops connected in series; Each of the flip-flops may receive an input terminal for receiving data, a positive output terminal for outputting a positive output signal, a negative output terminal for outputting a negative output signal complementary to the positive output signal, a clock terminal, and a reset signal. And a reset terminal for each flip-flop, wherein the sub-output terminal of each flip-flop is connected to the input terminal of a corresponding flip-flop and to the clock terminal of a next flip-flop, in response to at least two selection control signals. Selecting means for selectively outputting any one of the positive output and sub output signals of the flip-flops; Including the reset generating means for generating the reset signal by logically combining the selected signals, it is possible to freely control the counter reset signal generated therein, and to reduce the occurrence rate of the abnormal signal.

Description

Asynchronous counter circuit

The present invention relates to an asynchronous counter circuit, and more particularly, to an asynchronous counter circuit that can reduce an abnormal signal by complementing an asynchronous counter by a reset.

First of all, the counter can be largely divided according to the counting method and the operation clock pulse application method, and among these, the counter is divided into a synchronous counter and an asynchronous counter according to the input method of the operation clock pulse.

The synchronous counter is a method in which an input clock pulse synchronizes the clock values of each stage at the same time, and the asynchronous counter is a method in which the input clock pulse is affected by the output value of the previous stage.

The conventional asynchronous counter circuit is a reset asynchronous N-gin counter circuit using a reset / set flipflop (R / S flipflop).

The reset asynchronous N-count counter circuit is a counter circuit that returns to 0 after performing from 0 to N-1, and the state values therebetween are 0 to N-1, that is, N states.

Therefore, when the count reaches N while counting, all bits of the counter are reset and initialized to zero.

1 is a conventional asynchronous counter circuit.

Referring to Fig. 1, the conventional asynchronous counter circuit includes a counter means 10, a reset generating means 20, and a reset detecting means 30.

The counter means 10 outputs a previous signal through the output terminal Q in response to a predetermined clock CLK input from the outside (OUT1), and outputs an inverted signal with respect to the previous signal through the output terminal QN. In response to the inverted signal of the first flip-flop 12 and the first flip-flop 12 feeding the inverted signal back to the input terminal D, the previous signal is output through the output terminal Q (OUT2) A second flip-flop 14 for outputting an inverted signal with respect to the previous signal through the terminal QN, and in response to an inverted signal of the second flip-flop 14 and a second flip-flop 14 for feeding the inverted signal back to the input terminal D A third flip-flop 16 for outputting a previous signal through terminal Q (OUT3), outputting an inverted signal for the previous signal through output terminal QN, and returning the inverted signal to input terminal D again. .

At this time, the first, second, and third flip-flops 12, 14, and 16 are D-flip flops, each of which has a predetermined low level (from the reset detecting means 30 to the reset terminal RN). low level) signals are reset.

Next, the reset generating means 20 is an exclusive OR gate (XOR), and each of the previous signals from the output terminals Q of the first, second, and third flip-flops 12, 14, and 16, respectively. Is inputted, and it is detected whether the input signal coincides with a high level signal or a low level signal, respectively, and as a result of the detection, when each output signal matches with a high level signal or a low level signal, a predetermined low Output the level signal.

On the other hand, the reset detecting means 30 receives the predetermined low-level signal from the reset generating means 20 and receives the first, second, and third flip-flops 12, 14, and 16. Predetermined reset signals are respectively output to the first, second, and third flip-flops 12, 14, and 16, respectively.

The reset detecting means 30 includes a first NAND gate 32 having a first input terminal A connected to an output terminal of the reset generating means 20 as a reset-set flip-flop, and the first NAND gate. A first input terminal A is connected to an output terminal Y of 32, a second input terminal B is connected to a clock terminal that receives the clock CLK from the outside, and the first NAND gate. It consists of a 2nd NAND gate 34 connected with the output terminal Y to the 2nd input terminal B of (32).

In this case, the output terminal Y of the second NAND gate 34 is connected to the reset terminals RN of the first, second, and third flip-flops 12, 14, and 16, respectively.

When a low level coincidence signal output from the reset generating means 20 is input to the reset-set flip-flop, an asynchronous counter is designed in which the output signal of the reset-set flip-flop resets the counter of N bits. do.

The conventional asynchronous counter circuit using a reset-set flip-flop has a high probability of generating an abnormal signal such as a hazard.

The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide an asynchronous counter circuit in which an abnormal signal is hardly generated.

1 is a conventional asynchronous counter circuit diagram;

2 is an asynchronous counter circuit diagram in accordance with an embodiment of the present invention;

3 is a waveform diagram of an asynchronous counter circuit in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 50: counter means 20, 70: reset generating means

30, 40: reset detection means 32: first NAND gate

34: second NAND gate 60: selection means

12, 52: first flip-flop 14, 54: second flip-flop

16, 56: third flip-flop 62: first multiplexer

64: second multiplexer 66: third multiplexer

68: signal generating means

According to a feature of the invention proposed to achieve the above object, an asynchronous counter circuit comprises: counter means for generating at least two bits of binary coefficient output signals in response to an external clock; The counter means has at least two D-flip flops connected in series, each flip-flop having an input terminal for receiving data, a constant output terminal for outputting a constant output signal, and complementary to the constant output signal. A sub-output terminal for outputting a sub-output signal, a clock terminal, and a reset terminal for receiving a reset signal, wherein the sub-output terminal of each flip-flop is connected to the input terminal of the corresponding flip-flop and the next flip-flop Selection means connected to the clock terminal of and selectively outputting any one of the positive and negative output signals of the respective flip-flops in response to at least two selection control signals; Reset generating means for generating the reset signal by logically combining the selected signals.

In a preferred embodiment of this aspect, it further comprises reset detection means for receiving said reset signal and an external reset signal and for resetting said flip-flops when either one of said two reset signals is activated.

In a preferred embodiment of this aspect, the selection means receives the positive output and the sub output signals respectively output from the counter means, and outputs any one of the input signals to the reset generating means, respectively. Multiplexers; And signal generation means for generating the selection control signals to cause the multiplexers to output one of the positive output signal and the negative output signal.

In a preferred embodiment of this aspect, the reset generating means is a logic gate that generates the low level reset signal when the respective signals input from the selection means coincide with the high level signal.

According to another feature of the present invention, a predetermined level signal having a predetermined level signal received from the outside and a predetermined level signal from the inside, and a predetermined level signal received from the outside or a predetermined level signal received from the inside have a reset function. Reset detection means for outputting a predetermined reset signal in the case of a signal of? Counter means for outputting a previous signal for a predetermined input signal and an inverted signal for the previous signal in response to a clock input from the outside, and receiving and resetting the predetermined reset signal; Selecting means for selecting and outputting each one of each of the previous signal received from the counter means and an inverted signal with respect to the previous signal; A reset which receives the respective signals selected and outputted from the selection means and outputs a signal of a predetermined level to the reset detection means for resetting the counter means when each of the received signals coincides with a signal of a predetermined level; Generating means;

The present invention relates to an asynchronous counter circuit, comprising: counter means for generating at least two bits of binary coefficient output signals in response to an external clock, the counter means having at least two D-flip flops connected in series; Each of the flip-flops may receive an input terminal for receiving data, a positive output terminal for outputting a constant output signal, a negative output terminal for outputting a negative output signal complementary to the constant output signal, a clock terminal, and a reset signal. And a reset terminal for each flip-flop, wherein the sub-output terminal of each flip-flop is connected to the input terminal of a corresponding flip-flop and to the clock terminal of a next flip-flop, in response to at least two selection control signals. Selection means for selectively outputting any one of the positive output and sub output signals of the respective flip-flops; By logically combining the selected signals including a reset generating means for generating the reset signal, it is possible to freely control a reset input signal, it is possible to reduce the error signal rate.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 3.

2 is an asynchronous counter circuit according to an embodiment of the present invention.

Referring to FIG. 2, the asynchronous counter circuit according to the embodiment of the present invention includes a counter means 50, a selection means 60, and a reset generating means 70, and additionally reset detection means 40. ).

The counter means 50 generates at least two bits of binary coefficient output signals in response to an external clock CLK.

The counter means 50 comprises at least two D-flip flops 52, 54, 56 connected in series, each flip-flop 52, 54, 56 receiving data. Input terminal (D) for output, constant output terminal (Q) for outputting constant output signal, negative output terminal (QN), clock terminal (CK) and reset signal for outputting negative output signal complementary to the constant output signal. And a reset terminal (RN) for receiving a voltage, wherein the sub-output terminal (QN) of each flip-flop is connected to the input terminal (D) of the corresponding flip-flop and the clock terminal (CK) of the next flip-flop. Is connected to.

Here, the first flip-flop 52 outputs a positive output signal for a predetermined input signal and a negative output signal complementary to the positive output signal in response to the clock CK, and feedbacks the negative output signal. The input signal, and receives a predetermined reset signal from the reset detecting means (40).

The second flip-flop 54 outputs a predetermined positive output signal and a sub-output signal complementary to the positive output signal in response to the negative output signal of the first flip-flop 52. The output signal is fed back to be an input signal, and a predetermined reset signal is received from the reset detecting means 40.

In addition, the third flip-flop 56 outputs a predetermined constant output signal and a sub-output signal complementary to the positive output signal in response to the sub-output signal of the second flip-flop 54. The signal is fed back as an input signal and receives a predetermined reset signal from the reset detecting means 40.

Next, the selection means 60 selectively selects any one of the positive and negative output signals of the respective flip-flops 52, 54, 56 in response to at least two selection control signals SOS2. It has a function to output, and includes first, second, and third multiplexers 62, 64, 66, and signal generating means 68.

Here, the multiplexers 62, 64, and 66 receive the positive and negative output signals output from the counter means 50, respectively, to the respective input terminals D1 and D0, and the received signals. Any one of the signals is output to the reset generating means 70, respectively.

The signal generating means 68 may include any one of the constant output signal and the sub output signal complementary to the constant output signal to the first, second, and third multiplexers 62, 64, and 66, respectively. Generate predetermined selection control signals S0S2 for outputting one signal, and each of the above select terminals S of the first, second, and third multiplexers 62, 64, 66, respectively. A signal generator such as a predetermined register or a dip switch that outputs the select control signals S0S2.

Subsequently, the reset generating means 70 has a function of generating the reset signal by logically combining the selected signals, and the first, second, and third multiplexers 62, 64, 66. A predetermined low level signal for resetting the counter means 50 when the respective signals selected and output according to the selection control signals SOS2 are input, and the received signals coincide with a high level signal. Is a NAND gate for outputting to the reset detection means (40).

On the other hand, the reset detection means 40 receives the reset signal and the external reset signal (reset), when the one of the two reset signal is activated the first, second and third flip-flop 52 54 and 56 are AND gates for resetting.

In this way, the reset detection means 40 ANDs the low level signal, which is an input coincidence signal output from the reset generation means 70, and the external reset signal reset that can be controlled externally, and resets the low level reset signal. By outputting this, we implement an asynchronous counter circuit that is reset at the desired N-count counter.

In addition, when the external reset signal reset is applied as a low level signal, regardless of the input signal from the reset generating means 70, the two signals are ANDed to output a low level reset signal. You can reset it arbitrarily.

The following is a truth table of possible cases that the selection signal SOS2 may have.

TABLE 1

N S2 S1 S0 0 0 0 0 One 0 0 One 2 0 One 0 3 0 One One 4 One 0 0 5 One 0 One 6 One One 0 7 One One One

Referring to Table 1, the selection signal S2 is the most significant bit, it is possible to implement an N-count counter to freely select the time point to be reset according to the selection signal (S0S2).

3 is a waveform diagram of an asynchronous counter circuit according to an embodiment of the present invention.

Referring to FIG. 3, a low level signal is input to the counter means 50 according to the low level external reset signal, and the first and second, and according to a clock CLK input from the outside. The third flip-flops 52, 54, 56 sequentially generate respective output signals OUT1 OUT3.

Each of the two output signals output from the first, second, and third flip-flops 52, 54, 56, that is, the positive output signal and the sub-output signal complementary to the positive output signal, respectively, is the first output signal. The first and second and third multiplexers 62, 64, and 66 are inputted, and either of these two input signals is inputted to the selection control signals S0S2 input to the respective selection terminals S. According to each selected output.

Herein, when the selection control signals S0S2 are N as 5 as shown in Table 1, that is, the two selection signals S0 and S2 are the high level signal 1 and the other selection signal S1 is the same. As the low level signal 0, it is input to the first, second and third multiplexers 62, 64 and 66, respectively, and operates as a binary counter.

On the other hand, when the selection control signals S0S2 are high level signals, that is, when N is 7, the operation is performed as a seventh counter.

The asynchronous counter circuit described above is an asynchronous counter circuit designed using a multiplexer. The asynchronous counter circuit has a lower probability of generating an abnormal signal than a conventional counter-circuit using a reset-set flip-flop. Using the x1 multiplexer, it can be operated as a portable asynchronous counter that can implement up to hexadecimal asynchronous counters, and its use can be used quite widely.

The present invention solves the problem that the asynchronous counter circuit using a conventional reset-set flip-flop has a relatively high probability of generating an abnormal signal, and can freely control the counter reset signal generated internally, There is an effect that can be reduced.

Claims (5)

Counter means (50) for generating at least two bits of binary coefficient output signals in response to an external clock (CLK); The counter means 50 has at least two D-flip flops 52, 54, 56 connected in series, each of the flip-flops 52, 54, 56 having an input terminal for receiving data. (D) receiving a positive output terminal Q for outputting a constant output signal, a negative output terminal QN for outputting a negative output signal complementary to the constant output signal, a clock terminal CK, and a reset signal; And a reset terminal (RN) for connecting the sub-output terminal (QN) of each flip-flop to the input terminal (D) of the corresponding flip-flop and to the clock terminal (CK) of the next flip-flop. , Selection means (60) for selectively outputting any one of the positive and negative output signals of the respective flip-flops (52, 54, 56) in response to at least two selection control signals (S0S2); And a reset generating means (70) for generating the reset signal by logically combining the selected signals. The method of claim 1, And additionally detecting reset means (40) for receiving the reset signal and an external reset signal (reset) and for resetting the flip-flops (52, 54, 56) when either one of the two reset signals is activated. Asynchronous counter circuit. The method of claim 1, The selecting means 60 receives the positive output and the negative output signals Q and QN respectively output from the counter means 50, and outputs any one of the input signals to the reset generating means ( Multiplexers 62, 64, and 66 respectively output to 70; Signal generating means for generating the selection control signals S0S2 such that each of the multiplexers 62, 64, 66 outputs any one of the positive and negative output signals Q, QN; Asynchronous counter circuit. The method of claim 1, And the reset generating means (70) is a logic gate that generates the low level reset signal when each of the signals inputted from the selecting means (60) matches the high level signal. A predetermined reset signal when a predetermined level signal is input from the outside and a predetermined level signal from the inside, and the predetermined level signal from the outside or the predetermined level signal received from the inside is a predetermined level signal having a reset function Reset detection means (40) for outputting; In response to the clock CLK input from the outside, the previous signal Q for the predetermined input signal D and the inversion signal QN for the previous signal Q are outputted, and the predetermined reset signal is input. Counter means (50) that is received and reset; Selecting means (60) for selecting and outputting any one of each of the previous signal (Q) received from the counter means (50) and an inverted signal (QN) with respect to the previous signal (Q); Receives the respective signals selected and output from the selection means 60, and resets the signal of the predetermined level for resetting the counter means 50 when the respective received signals coincide with the signals of the predetermined level. An asynchronous counter circuit comprising reset generating means (70) output to the detecting means (40).