JPH0271638A - Timing signal generator - Google Patents

Abstract

PURPOSE:To devise the generator such that an internal timing signal rises quickly by providing a frequency detecting means and constituting a converting point detection means so as to generates a trigger pulse when the frequency detection means generates a detection signal. CONSTITUTION:The converting point detection means 1 detects a leading conversion point of an external timing signal having a frequency being a half or an integral number of multiple of an internal timing signal to generate a trigger pulse. An internal timing generating means 2 receiving the trigger pulse raises the internal timing signal. Moreover, the frequency detecting means 3 detects it that the frequency of the timing signal of an external device is a half that of the internal timing signal and generates the detection signal to the means 1. When the means 3 generates a detection signal, the means 1 outputs the trigger pulse to the means 2 in the first leading timing or trailing timing. Thus, the chance able to raise the internal timing signal is doubled and the internal timing signal is raised quickly.

Description

DETAILED DESCRIPTION OF THE INVENTION (Summary) Conversion inspection that relates to a timing signal generator and in particular detects the rising transition point of a timing signal from an external device whose frequency is half or an integral multiple of an internal timing signal and generates a trigger pulse. The present invention relates to a timing signal generation device having internal timing generation means for receiving the trigger pulse and generating the internal timing signal, and for generating the internal timing signal quickly even when synchronizing with an external timing signal having a lower frequency than the internal timing signal. conversion point detection means for detecting the rising transition point of a timing signal of an external device having a frequency that is half or an integral multiple of the internal timing signal and generating a trigger pulse; and an internal timing generation means for raising the internal timing signal in response to a trigger pulse of A detecting means is provided, and the conversion point detecting means is configured to generate a trigger pulse at the first rising timing or falling timing when the frequency detecting means generates the detection signal.

(Industrial Application Field) The present invention relates to a timing signal generator, and more particularly, to a timing signal generator that generates a half of the internal timing signal of an external device connected to the device.
Or a timing having a conversion point detection means for detecting a rising conversion point of a timing signal of an external device having an integral multiple frequency and generating a trigger pulse, and an internal timing generation means for receiving the trigger pulse and generating the internal timing signal. This invention relates to a signal generator.

For example, when a device such as a modulator/demodulator sends and receives data to and from an external device, it synchronizes the timing signal inside the device with the timing signal of the external device, and generates data that is synchronized with these timing signals. Perform giving and receiving. Here, as shown in Fig. 4, the frequency of the external timing signal is the same as the frequency f of the internal timing signal (Fig. 4 (C)) or an integral multiple (Fig. 4 (a), (b), (C)).
) or half - (Figure 4(d)).

(Prior Art) As the above-mentioned timing signal generating device, there is one shown in FIG. This is a conversion point detection means 1 that detects the rising edge of an external timing signal and generates a trigger pulse.
1, and internal timing generating means 12 which receives the trigger pulse generated by this conversion point detecting means 11 and generates an internal timing signal.

With such a timing signal generator, as shown in FIG. 4, it is possible to obtain an internal timing signal that is synchronized with the rising edge of an external timing signal, and data can be sent and received normally.

(Problem to be Solved by the Invention) By the way, as mentioned above, some external timing signals have the frequency f of the internal timing signal - half, but it is not possible to synchronize the internal timing signal with such an external timing signal. If you try to do this, the rise of the internal timing signal may be delayed. This is because the conventional timing signal generator described above synchronizes the rising edge of the internal timing signal with the rising edge of the external timing signal.
This is because, as shown in the figure, if an attempt is made to raise the internal timing signal when the external timing signal is in a high state, it is necessary to wait until the next external timing signal rises.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a timing signal generating device that can quickly raise an internal timing signal even when synchronizing with an external timing signal having a lower frequency than the internal timing signal.

(Means for solving the problems) In the present invention, the means for solving the above problems are as follows:
As shown in FIG. 1 as a principle diagram of the present invention, a conversion point detection means 1 detects a rising conversion point of an external timing signal having a frequency that is half or an integral multiple of the internal timing signal and generates a trigger pulse; In a timing signal generating device having an internal timing generating means 2 which receives this trigger pulse and raises the internal timing signal, it detects that the timing signal of the external device is one-half of the internal timing signal and generates a detection signal. In addition, the conversion wheel detecting means 1 is configured to generate a trigger pulse at the first rising timing or falling timing when the frequency detecting means 3 generates a detection signal.

(Function) According to the present invention, the frequency detection means 3 generates a detection signal when the frequency of the external timing signal is - half of the internal timing signal, and the conversion point detection means 1 generates a detection signal at the first rising timing or falling edge of the generated timing signal. Since the trigger pulse is outputted to the internal timing signal means at the appropriate timing, there are only two chances to raise the internal timing signal, and the internal timing signal can be raised quickly.

(Example) An example of a timing signal generator according to the present invention will be described below based on the drawings.

FIG. 2(a) is a configuration diagram of an embodiment of the present invention.

In this embodiment, the timing signal generating device includes an internal timing generating means 2 that generates an internal timing signal of a predetermined frequency f by inputting a trigger pulse, and an external timing signal that receives an external timing signal and whose frequency is determined by the internal timing signal. Frequency detection means 3 generates a detection signal when the frequency is half of the frequency of the internal timing signal generated by generation means 2; When the frequency detection means 3 generates a detection signal,
The converting point detecting means 1 detects the first rising or falling edge of an external timing signal and outputs a trigger pulse.

The conversion detection means 1 includes a rise detection section 1a, a rise/fall detection section 1b, and an AND gate lc.

ld, OR gate le, flip-flop circuit Ig, l
h. Although not shown, a delay circuit that delays an input external timing signal by a predetermined period ΔT and an inversion circuit that inverts the output of this delay circuit are provided, and the input external timing signal and the output of the above-mentioned inversion circuit are provided. By inputting this into an AND gate (not shown), a pulse having a pulse width ΔT can be obtained at the time of the rise of the external timing signal (this pulse becomes the output pulse of the rise detection section 1a). By inputting the output signal of the circuit and the aforementioned external timing signal to an exclusive OR gate (E-OR gate) not shown, the output pulse of this exclusive OR gate is generated at the rising and falling points of the external timing signal. This becomes a pulse having a pulse width ΔT, and this pulse becomes the output pulse of the rise/fall detection section 1b described above.

The frequency detection means 3 includes an AND gate 3a and A which receives an external timing signal and a main clock pulse PM.
A counter 3b that counts the number of pulses output from the ND game) 3a, and an AND gate 3ct + 3C2* 3 (3, as
s and AND gates 3c, 3c3. ..., and an OR gate 3e that receives the output signal of the OR gate 3d and the output signal of the AND gate 3C□.

The output signal of the AND gate 3c is also input to the flip-flop circuit 1h, and the output signal of the OR gate 3d is also input to the flip-flop circuit 1g. The counter 3b counts the number of main clock pulses during the period when the external timing signal is at H level.

Therefore, the frequency of the external timing signal can be determined from the count value of the counter 3b, that is, the signal appearing at the output terminal.

Letting f be the frequency of the external timing signal when the H level pulse signal is output from the AND gate 3c2,
When the H level pulse signal is output from the AND gate 3c, the external timing signal is output from the AND gate 3c, .
3c,,ac3. "3f..." is the frequency of the external timing signal.

An H level pulse signal is input to the flop circuit 1h, and an H level pulse signal is input to the flop circuit 1g.

Note that AND gates 3c, 3c2, 3c3 . When an H level pulse signal is input from ..., OR gate 3
A high level pulse signal is input from e to counter 3b.
, the count value of counter 3b becomes “O11”.
becomes.

The internal timing generating means 2 generates a main clock pulse P.
A frequency dividing circuit 2a is provided which divides the frequency of M and outputs an internal timing signal of frequency f.

(b) When the frequency of the external timing signal is an integral number n times the frequency of the internal timing signal (n=1.2...).

AND gate 3c2゜3C3,... of frequency detection means 3
When an H level pulse signal is output from either of the above, the flip-flop circuit 1g passes through the OR gate 3d.
is input to.

The flip-flop circuit 1g receives this H level pulse signal and outputs an H level pulse signal. This H
The level signal is held thereafter.

On the other hand, the rising edge detection section 1a outputs an H level pulse signal at the rising edge of the external timing signal as described above, so this H level pulse signal is passed through the OR gate 1e to the frequency division of the internal timing generating means 2. It is input as a trigger pulse to circuit 2a.

Since the frequency dividing circuit 2a starts frequency dividing operation every time this trigger pulse is input, the phases of the external timing signal and the internal timing signal match.

(b) When the frequency of the external timing signal is -half the frequency of the internal timing signal.

The internal timing signal rises in synchronization with the first rise or fall of the input external timing signal. This point will be explained below.

As mentioned above, the AND gate 3c of the frequency detection means 3,
Since an H level pulse signal is output from the flip-flop circuit 1h, the flip-flop circuit 1h receives this H level pulse signal and outputs an H level signal. This H level signal is held thereafter.

On the other hand, since the rising/falling detection section 1b outputs an H level pulse signal at the rising and falling points of the external timing signal as described above, this H level pulse signal is passed through the OR gate 1e. , is input as a trigger pulse to the frequency dividing circuit 2a of the internal timing generating means 2.

Since the frequency dividing circuit 2a starts frequency dividing operation every time this trigger pulse is input, the internal timing signal is synchronized with the first falling edge of the input external timing signal, as shown in FIG. 2(b). and stand up.

Note that even when the rising edge of the external timing signal input to the conversion point detection means 1 appears first, the internal timing signal output from the internal timing generation means 2 similarly rises in synchronization with this rising edge. .

Therefore, according to the timing signal generating device according to this embodiment, when the frequency of the external timing signal is an integral number n times the frequency of the internal timing signal (n=1°2, . . . ), the external timing The internal timing signal rises in synchronization with the rising edge of the signal, while when the frequency of the external timing signal is - half the frequency of the internal timing signal, the internal timing signal rises in synchronization with the rising edge or falling edge of the first external timing signal. Raise the signal. Therefore, as shown in Figure 2 (b) (1) and (2), the frequency of the external timing signal is - half that of the internal timing signal, and when the external timing signal is in the high state, the internal signal does not rise. In this case, the internal timing signal rises in synchronization with the first fall of the external timing signal, so that the internal timing signal can rise earlier than the next rise of the external timing signal. In addition, in this embodiment, when the external signal is in a low state, the internal timing signal is raised in synchronization with the rising of the external timing signal, as in the conventional case. The internal timing signal can be raised within a time period that is half the period of the external timing signal.

(Effects of the Invention) As explained above, according to the present invention, the timing signal generating device detects that the frequency of the timing signal of the external device is one-half of the internal timing signal and generates the detection signal. In addition, since the conversion point detection means is configured to generate a trigger pulse at the first rising timing or falling timing when the frequency detection means generates a detection signal, there is no opportunity for the internal timing signal to rise. is 2 minutes, which has the effect that the internal timing signal can be raised quickly.

[Brief explanation of the drawing]

Figure 1 is a principle diagram of the present invention, Figure 2 (a) is a configuration diagram of an embodiment of the present invention, Figure 2 (b) is a signal waveform diagram explaining the operation of the implementation, and Figure 3 is a conventional timing signal generation diagram. FIG. 4 is a block diagram showing the configuration of the device, FIG. 4 is a diagram showing the types of timing signals, and FIG. 5 is a diagram explaining problems with the conventional timing signal generating device. 1... Conversion point detection means 2... Internal timing generation means 3... Frequency detection means

Claims (1)

[Claims] Conversion point detection means (1) for generating a trigger pulse by detecting a rising conversion point of an external timing signal having a frequency that is one-half or an integral multiple of the internal timing signal; In the timing signal generation device having internal timing generation means (2) for raising the internal timing signal, a frequency detection device generates a detection signal by detecting that the frequency of the external timing signal is one-half of the internal timing signal. In addition to providing means (3), the conversion point detecting means (
1) A timing signal generating device characterized in that when the frequency detecting means (3) generates a detection signal, a trigger pulse is generated at the first rising timing or falling timing.