JPH0119299B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an oscillation stop detection circuit system.

As shown in FIGS. 1 and 2, the conventional oscillation stop detection circuit focuses on the gap T ₁ between the output pulse signal b of the frequency multiplier 3 and the discharge time constant T 2 determined by the capacitor 1 and resistor ₂ . However, as shown in Figure 2, αT ₁ ≧T ₂ (However, α is the margin coefficient.)
It is determined that oscillation has stopped under the following conditions. The key point in the design of this circuit is the setting of the discharge time constant T ₂ , and its minimum value must be set in consideration of various dispersion factors. especially,
In the design of CMOS integrated circuits, the output pulse gap T ₁ is selected to be approximately 1/1000 to 1/10000 seconds in order to suppress current consumption, so the discharge time constant T ₂ is required to be 10/1000 to 1/1000 seconds. However, considering manufacturing process variations, temperature characteristics, etc., a considerable amount of space is required in terms of design dimensions, which is a bottleneck in terms of IC integration.

The present invention eliminates this problem by applying a digital method to monitor the pulse gap and adjusting the time constant.
The aim is to reduce T ₂ and make the area occupied by the pattern more compact.

The present invention will be described in detail below based on Examples.

FIG. 3 is a logic circuit diagram of the oscillation stop detection circuit according to the present invention, and FIG. 4 shows a timing chart of main signals for a half period of the oscillation monitor signal. In terms of blocks, it consists of a retrigger type monostable multivibrator circuit 4, a pulse generation circuit 5, a preset type town counter circuit 6, and a power-on pulse generation circuit 7.

The oscillation monitoring signal e obtained based on the oscillation output of the oscillation circuit is a differential pulse signal. This pulse is ORed with the output signal f of the power-on pulse generation circuit 7, and becomes the g signal. The g signal becomes the input trigger signal h of the retrigger type monostable multivibrator circuit 4 via the OR gate circuit, and the monostable multivibrator starts operating. Multivibrator circuit 4 has V _DD
- A resistor 9 and a transistor connected in series between V _SS and a capacitor 8 connected to this series connection point.
It consists of A signal i is output during a period when the capacitor 8 is charged by the input trigger signal h and then discharged via the resistor 9.

That is, as shown in FIG. 4, the pulse width of the output signal i is determined by the time constant determined by the capacitor 8 and the resistor 9.
Specified in T ₃ . The retrigger type monostable multivibrator circuit 4 shown in FIG. 3 guarantees an output pulse signal i from the falling edge of the input trigger signal h in all time intervals.

Output signal i of monostable multivibrator circuit
is input to the pulse generation circuit 5. The configuration of the pulse generation circuit 5 is such that a time constant determined by a capacitor 13 and a resistor 12 defines the delay time from the falling edge of the output signal i of the monostable multivibrator circuit 4, and the pulse width is determined by a time constant determined by a capacitor 13 and a resistor 12. The time constant is specified by diode 11
In this case, the input signal of the next stage buffer gate 14 is V _SS
This is to clamp the voltage level that drops below the potential. That is, the function of the pulse generating circuit 5 is to generate a differential pulse j having an appropriate phase delay with respect to the falling edge of the output signal i of the monostable multivibrator circuit 4, as shown in FIG. This output signal j becomes the trigger signal h via the OR circuit and is input to the monostable multivibrator circuit 4, so that the signal i is output again.

The signal j is also input to a preset type down counter circuit 6. Down counter circuit 6
is composed of a preset type master-slave type flip-flop circuit 18. The oscillation monitor signal g is input to the set terminal of the flip-flop circuit 18. The down counter circuit 6 is preset to "3" by this signal g, and the fourth
As shown in the figure, both the signals k and l become high level, and the output signal m also becomes high level. After this,
A signal j is input as a clock from the pulse generating circuit 5, and the preset "3" is counted down. This flip-flop circuit 18 receives the signal j
The output Q is inverted at the falling edge of . When the first signal j is input, the signal k becomes low level at the falling edge of the signal j. At this time, the signal l remains at high level. Next, when signal j is input, signal k becomes high level and signal l becomes low level. When the third signal j is input, the signals k and l become low level. This count value is 0
, that is, when both output signals k and l become low level, output signal m becomes low level. The output of the pulse generating circuit 5 is ANDed with this signal m. Therefore, when the signal m becomes low level, the pulse output of the output signal j of the pulse generating circuit 5 is prohibited. The gate circuit that takes the AND of both signals functions as an inhibition gate circuit for signal j.

That is, the point of the present invention lies in the operation circuit of the retrigger type monostable multivibrator circuit 4. If the number of times the preset down counter circuit 6 has been preset is N times, then N+1.
This is due to repeated rotations. In the case of FIG. 3, N=3. The monostable multivibrator circuit 4 first operates upon receiving an oscillation monitor signal. As a result, the signal j is outputted, the monostable multivibrator circuit 4 operates again, and the second signal j is outputted. At the time when the third signal j is output, the output m of the counter circuit 6 becomes low level, and subsequent output of the signal j is prohibited. Therefore, as a result, monostable multivibrator circuit 4
is 4 due to the four trigger signals of signal g and signal j.
It will work twice. When the fourth operation is completed, the output signal i is at a low level, the output m of the counter circuit is at a low level, the output of the NOR circuit serving as an output gate circuit is at a high level, and an oscillation stop detection signal n is output.

In the present invention, when the oscillation monitor signal g arrives before the down counter circuit 6 finishes down counting, the counter circuit 6 is preset again and the output signal m remains at a high level, and the oscillation is stopped. No stop detection.

In addition, the power-on pulse generation circuit 7 in FIG.
A time delay from the power-on timing is set by the capacitor 17 and the resistor 16, and a pulse is generated by this delay. diode 15
This shortens the discharge time of the capacitor 17 when the power is cut off, and ensures reliable generation of the power-on pulse.

In this method, the down counter circuit 6 is initialized when the power is turned on by pseudo-generating the output signal of the frequency multiplier circuit 3 using the output signal f of the power-on pulse generation circuit 7. It's on.

As mentioned in the above explanation of the operation, the effect of the present invention is to set the number of counters N, thereby extending the time constant _T3 determined by the monostable multivibrator circuit 4, and to obtain an apparent time constant T= (N+
1) It is possible to make ×T ₃ . Although the circuit configuration is more complicated than that shown in FIG. 1, it is mainly composed of gates, and the values of the capacitor and resistor have a time constant on the order of 1 microsecond, which is a considerable reduction in design dimensions.

Furthermore, the advantage of this method is that the monostable monomulti circuit 4 does not always operate by the number set in the down counter circuit 6, but is initialized by the oscillation monitor signal e during the countdown. It is. Based on the design concept, this is the time constant of monostable multivibrator circuit 4.
_T3 is set to be equal to or less than the period of the oscillation monitor signal, and the number of bits of the down counter circuit 6 ensures that variations in various characteristics such as manufacturing and temperature can be absorbed. Therefore, the number of times of charging and discharging is not fixed at the maximum, and the increase in current consumption is also alleviated.

Furthermore, in the conventional case, sudden power fluctuations due to heavy loads were detected by one level comparison, but in the case of the present invention, oscillation stop is detected by the output signal m of the down counter circuit 6. Since the signal is masked, it is effective in preventing malfunctions.

Possible applications include monitoring oscillation circuits in watch control circuits. In addition, especially when there are large fluctuations in the power supply of heavy loads such as lithium battery power supply,
It can be used as an oscillation stop detection circuit without malfunction.

[Brief explanation of drawings]

1 and 2 are a circuit diagram and a timing chart of a conventional example, and FIGS. 3 and 4 are a circuit diagram and a timing chart of an embodiment of the present invention. 1 is a capacitor, 2 is a resistor, 3 is a frequency multiplier circuit, 4 is a retrigger type monostable multivibrator circuit, 5 is a pulse generation circuit, 6 is a preset type down counter circuit, 7 is a power-on pulse generation circuit, 8, 10, 13, 17 are capacitors, 9,
12 and 16 are resistors, and 11 and 15 are diodes. Note that each logic gate symbol shown in Figure 3 is
Although it conforms to the MIL standard, 18 is a preset type master-slave type flip-flop circuit.

Claims (1)

[Claims] 1. An OR gate circuit having two input terminals and inputting an oscillation monitor signal obtained based on the oscillation output of the oscillation circuit to one input terminal, and at least a resistor and a capacitor. a monostable multivibrator circuit that receives the output signal of the OR circuit and outputs a first signal having a pulse width corresponding to the time constant of the resistor and the capacitor;
a pulse generating circuit that inputs and delays a signal and outputs a second signal, which is a differential pulse, to the other input terminal of the OR circuit after the input of the first signal is completed; a counter circuit which counts the second signal which is preset and is output from the pulse generation circuit for the predetermined number of times and whose output signal is logically inverted; a prohibition gate circuit that prohibits the outputted second signal from being input to the OR gate circuit and the pre-counter circuit; and a prohibition gate circuit connected to each output terminal of the monostable multivibrator circuit and the counter circuit; An oscillation stop detection circuit comprising: an output gate circuit that outputs an oscillation stop detection signal when no signal is output and the output signal of the counter circuit is logically inverted.