JP3366223B2 - Multiplication circuit and timing adjustment circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing adjustment circuit for internal contacts of a semiconductor integrated circuit, and more particularly to a timing adjustment circuit for a multiplication circuit.

[0002]

2. Description of the Related Art A conventional well-known multiplication circuit is shown in FIG. The multiplication circuit of FIG. 4 includes a first inverter 7 that receives the reference clock CK, a second inverter 8 that receives the output of the inverter 7, a delay circuit 9 that receives the output of the inverter 8, and a delay circuit 9. A third inverter 3 which receives the output of the circuit 9 and an inverter 3
A second inverter 12 that receives the output of the reference clock CK, and a reference clock CK and the output of the inverter 12 that input 2
It has an input EXOR11.

The operation of this conventional multiplication circuit will be described with reference to the timing chart shown in FIG.

First, at time t0, the initial state of this multiplication circuit is represented. The reference clock CK, the output of the delay circuit 9, the output of the inverter 8 and the output of the 2-input EXOR 11 are low level, and the output of the inverter 3 is High level.

When the reference clock CK rises at time t1, the output of the 2-input EXOR 11 is inverted from low level to high level. Further, the output of the inverter 8 is also inverted from low level to high level, and the high level is input to the delay circuit 9. At this time, the output potential of the delay circuit 9 starts to rise gently. At time t2 when the output of the delay circuit 9 exceeds the logical threshold value of the inverter 3, the inverter 3 is inverted from the high level to the low level. As a result, 2-input EXOR
The output of 11 is inverted from high level to low level.

When the reference clock CK falls at time t3, the 2-input EXOR 11 is inverted from low level to high level, the output of the inverter 8 is also inverted from high level to low level, and the low level is input to the delay circuit 9. At this time, the output potential of the delay circuit 9 starts to fall gently. At time t4 when the output of the delay circuit 9 exceeds the logical threshold value of the inverter 3, the inverter 3 is inverted from the low level to the high level. As a result, the output of the 2-input EXOR 11 is inverted from high level to low level.

As described above, the multiplier circuit of FIG. 4 inputs the signal of the reference clock CK and the signal obtained by delaying the reference clock CK to the two-input EXOR 11, respectively, so that the frequency of the reference clock CK is doubled. The signal of is output.

[0008]

In the conventional multiplier circuit, when noise is superimposed on the power supply or GND while the delay element is being charged or discharged, the multiplier circuit is affected by the noise and the threshold of the logic circuit in the multiplier circuit is affected. Since the value fluctuates, there is a problem that a malfunction occurs.

Normally, the output of the multiplication circuit is the CPU, ROM,
It is often used as a clock for a functional block such as RAM and also shares a power supply and GND. Since that functional block operates at the rising and falling edges of the output of the multiplier circuit, a large current flows into the power supply or GND at that timing. . As a result, the power supply potential or the GND potential of the multiplication circuit is swung, and so-called power supply and GND noise is generated.
Also, at this timing, the delay element is being charged or discharged, so the threshold value of the inverter that receives the output of the delay circuit fluctuates due to the power supply or GND noise, causing a malfunction.

The above operation will be described with reference to the circuit diagram of FIG. 4 and the timing chart of FIG. First, at the time t1, the 2-input EXOR is received in response to the rise of the reference clock CK.
The output of 11 is inverted from low level to high level, and the output potential of the delay circuit 9 starts to rise gently. At this time, CPU, RO
Since the functional blocks such as M and RAM operate all at once, a current flows into the power supply or GND, and as a result noise occurs, the logic threshold value of the inverter 3 changes. However, since the output of the delay circuit 9 at this time is at the GND potential, the inverter receiving this output does not malfunction.

When the output of the delay circuit 9 exceeds the logical threshold value of the inverter 3 at time t2, the output of the inverter 3 is inverted from the high level to the low level, and the 2-input EXOR 11 is provided.
Is inverted from high level to low level. At this time, CPU, RO
Since the functional blocks such as M and RAM operate simultaneously, noise is generated in the power supply or GND. Furthermore, the delay circuit 9
Since the output potential of is near the threshold of the inverter 3,
When the threshold value of the inverter 3 fluctuates due to power supply or GND noise, a hazard occurs in the output of the inverter 3 as seen from time t2 to t4, and as a result, an unexpected clock is generated from the output of the multiplier circuit. Become.

The object of the present invention is to provide a power supply or GND as described above.
It is an object of the present invention to provide a timing adjustment circuit capable of preventing a malfunction of a multiplication circuit due to the influence of noise with a simple circuit configuration.

Another object of the present invention is to provide a multiplication circuit using such a timing adjustment circuit.

[0014]

The timing adjusting circuit of the present invention comprises an inverting delay circuit for giving a predetermined delay in order to shift the timing susceptible to noise, and a resistor and a capacitor within this delay time. And a feedback circuit for forcibly setting the output of the delay circuit to the power supply potential or the GND potential.

As a result, the output of the delay circuit composed of resistors and capacitors can be fixed to the power supply or GND near the rising and falling edges of the output of the multiplying circuit. A malfunction of the circuit can be prevented.

The multiplier circuit of the present invention inputs the first inverter circuit which receives the reference clock, the second inverter circuit which receives the output of the first inverter circuit and the output of the second inverter circuit. A delay circuit that gives a predetermined delay, a timing adjustment circuit that receives the output of the delay circuit as an input, gives a predetermined delay, and forcibly sets the output of the delay circuit to a power supply potential or a GND potential, and the reference clock And a two-input exclusive OR circuit having inputs of the output of the timing adjustment circuit and the exclusive O
The output of the R circuit multiplies the reference clock.

[0017]

1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

In the embodiment of the present invention, the reference clock CK is used.
To the input, a second inverter 8 to which the output of the inverter 7 is input, a delay circuit 9 including the output of the inverter 8 as an input and consisting of a resistor and a capacitor, and an output of the delay circuit 9 to the input And an inverting delay circuit 4 composed of an odd number (three in the figure) of inverters connected in series with the output of the inverter 3 as the input, and the output of the inverter 3 and the output of the inverting delay circuit 4. And a two-input OR5 having inputs as inputs, a two-input AND6 having an output from the inverter 3 and an output from the inverting delay circuit 4 as inputs, and
A P-channel MOS transistor 1 whose input is the output of the OR5 and whose output is connected to the output of the delay circuit 9, and an N-channel MOS transistor 2 whose input is the output of the 2-input AND6 and whose output is connected to the output of the delay circuit 9. , The reference clock CK and the output of the inverting delay circuit 4 are input 2
It has an input EXOR11.

Here, the inverter 3, the inverting delay circuit 4, the 2-input OR 5, the 2-input AND 6, and the P-channel MO.
S-transistor 1, N-channel MOS transistor 2
Constitute the timing adjustment circuit 10.

Now, the time t0 shown in FIG. 2 represents the initial state of this multiplication circuit, and the reference clock CK, the output of the inverter 8, the output of the delay circuit 9, the output of the inverting delay circuit 4, the output of the 2-input AND 6, 2 The output of the input EXOR 11 is at the low level, the output of the inverter 3 is at the high level, and the output of the 2-input OR 5 is at the high level. In response to the rising of the reference clock CK at time t1, the 2-input EXOR 11 is inverted from low level to high level, the inverter 8 is also inverted from low level to high level, and the high level is input to the delay circuit 9. At this time, the output potential of the delay circuit 9 starts to rise gently.

When the output of the delay circuit 9 exceeds the logical threshold value of the inverter 3 at time t2, the output of the inverter 3 is inverted from high level to low level, and the output of the 2-input OR5 is also inverted from high level to low level. , P channel M
The OS transistor 1 turns on. As a result, the delay circuit 9
The output of the _IC rapidly rises to the power supply potential V _DD . Further, since a predetermined delay is given by the inverting delay circuit 4, the time t
At the same time, the 2-input EXOR 11 is inverted from the high level to the low level at 3, and at the same time, the P-channel MOS transistor 1
Turns off.

Further, at time t3, CPU, ROM, RAM
Since functional blocks such as the above operate, a large current flows into the power supply or GND, noise is generated in the power supply or GND, and the logic threshold value of the inverter 3 fluctuates, but the output of the delay circuit 9 is already at the power supply potential. Since it has arrived, the inverter 3 does not malfunction.

At the time t4, the output of the 2-input EXOR 11 is inverted from the low level to the high level in response to the fall of the reference clock CK, and the output of the inverter 8 is also inverted from the high level to the low level, so that the delay circuit 9 is changed to the low level. Is entered. At this time, the output potential of the delay circuit 9 starts to fall gently.

When the output of the delay circuit 9 exceeds the logical threshold value of the inverter 3 at time t5, the output of the inverter 3 is inverted from low level to high level, and the output of the 2-input AND6 is also inverted from low level to high level. , N-channel MOS transistor 2 is turned on. As a result, the output potential of the delay circuit 9 rapidly drops to the GND potential.

Further, since a predetermined delay is given by the inverting delay element 4, the 2-input EXOR 11 changes from the high level to the low level at the time t6, and at the same time, the N channel M
The OS transistor 2 is turned off. Also, as described above,
At time t4, the functional blocks such as CPU, ROM, and RAM operate, so that noise occurs in the power supply or GND and the logic threshold value of the inverter 3 fluctuates, but the output of the delay circuit 9 has already reached the GND potential. Inverter 3
Does not malfunction.

Next, FIG. 3 is a circuit diagram showing the configuration of the second embodiment. In FIG. 3, the inverting delay circuit in the timing adjustment circuit of FIG. 1 is replaced with an inverting delay circuit 4 including a resistor and an odd number of inverters. Even such an inverting delay circuit operates similarly to the inverting delay circuit of FIG. Since the whole operation is the same as that in FIG. 1, the description is omitted.

[0027]

As described above, according to the present invention, the CPU, the RO
Even if the functional blocks such as M and RAM operate in synchronization with the clock output from the multiplier circuit to generate power supply or GND noise, the timing of the power supply or GND noise is shifted by the inverting delay circuit in the timing adjustment circuit. Further, since the output potential of the multiplication circuit is pulled up or pulled down by the power supply or GND by the feedback circuit, even if the power supply or GND noise is superimposed at this timing and the logic threshold value of the inverter fluctuates, A normal clock can be output.

For example, in a circuit including a CPU, a ROM and a RAM, if the power supply voltage is 3V and the threshold value of the inverter is 1.5V, even if noise of about 1.5V is superimposed on the power supply or GND, If the timing adjustment circuit is used, the clock output from the multiplication circuit can be stably supplied.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart for explaining an example of the operation of the circuit of FIG.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining an example of a conventional technique.

5 is a timing chart for explaining an example of the operation of the circuit of FIG.

FIG. 6 is a timing chart showing an example of an operation when the circuit of FIG. 4 malfunctions.

[Explanation of symbols]

1 P-channel MOS transistor 2 N-channel MOS transistor 3,7,8 CMOS inverter 4 Inversion delay circuit 5 2-input OR 6 2-input AND 9 Delay circuit 10 Timing adjustment circuit 11 2 input EXOR

   ─────────────────────────────────────────────────── ─── Continued front page       (56) Reference JP-A-6-152338 (JP, A)                 JP 63-54014 (JP, A)                 JP-A-63-10913 (JP, A)                 JP-A-4-104514 (JP, A)

Claims (6)

(57) [Claims] 1. A first inverter circuit that receives a reference clock, a second inverter circuit that receives the output of the first inverter circuit, and a predetermined inverter that receives the output of the second inverter circuit. A delay circuit including a resistance and a capacitance for giving a delay; a third inverter circuit having an output of the delay circuit as an input; an inverting delay circuit having an output of the third inverter circuit as an input and giving a predetermined delay; Two-input OR circuit and two-input A, which respectively have the output of the inverting delay circuit and the output of the third inverter circuit as inputs
An ND circuit, a P-channel MOS transistor whose output is connected to the input of the third inverter circuit, and which outputs the output of the 2-input OR circuit and forcibly sets the output of the delay circuit to a power supply potential; The output of the AND circuit is input and the output is the third
N-channel MOS transistor connected to the input of the inverter circuit and forcibly setting the output of the delay circuit to the GND potential, and a two-input exclusive OR circuit having the reference clock and the output of the inverting delay circuit as inputs And a multiplying circuit, wherein the output of the exclusive OR circuit multiplies the reference clock. 2. The multiplier circuit according to claim 1, wherein the inverting delay circuit is composed of an odd number of inverters. 3. The multiplier circuit according to claim 1, wherein the inverting delay circuit includes a resistor and an odd number of inverters. 4. An inverter circuit having an output of a delay circuit composed of a resistor and a capacitance as an input, an inverting delay circuit for giving a predetermined delay having an output of the inverter circuit as an input, and an output of the inverting delay circuit. A two-input OR circuit and a two-input AND circuit, each of which receives an output of the inverter circuit, and an output of the two-input OR circuit, which is connected to an input of the inverter circuit, forcing an output of the delay circuit P-channel MOS transistor that is set to a power supply potential, and an N-channel MOS transistor that receives the output of the 2-input AND circuit as an input and is connected to the input of the inverter circuit to forcibly set the output of the delay circuit to the GND potential A timing adjustment circuit comprising: 5. The timing adjusting circuit according to claim 4, wherein the inverting delay circuit is composed of an odd number of inverters. 6. The timing adjusting circuit according to claim 4, wherein the inverting delay circuit includes a resistor and an odd number of inverters.