JP5536633B2 - Edge detection circuit - Google Patents

Description

  The present invention relates to an edge detection circuit that outputs an edge detection signal in synchronization with a rising or falling edge of an input signal.

  As edge detection circuits, those shown in FIGS. 5 and 7 are known. In the edge detection circuit shown in FIG. 5, a differentiation circuit 3 including a capacitor C2 and a resistor R3 is connected to an output node N5 of a NOR circuit NOR1 whose one input side is connected to the signal input terminal 1. The signal of the node N6 is input to the inverter INV5, the output side of the inverter INV5 is connected to the signal output terminal 2, and the other input side of the NOR circuit NOR1 is connected.

  In this edge detection circuit, the signal output terminal 2 is always at a low level, and while the signal input terminal 1 is at a low level, the node N5 is at a high level and the node N6 is also at a high level. In this state, when the signal input terminal 1 rises to the high level, the node N5 becomes the low level. As a result, the potential of the node N6 rises with the time constant of the resistor R3 and the capacitor C2, and when the level exceeds the threshold value Vth5 of the inverter INV5, the output side of the inverter INV5 becomes high level. At the same time, the node N5 on the output side of the NOR circuit NOR1 becomes high level. In this manner, an edge detection signal synchronized with the rising edge of the input signal is obtained from the signal output terminal 2 at the signal input terminal 1.

  On the other hand, in the edge detection circuit shown in FIG. 7, one input side is connected to the signal input terminal 1, the other input side is connected to the signal input terminal 1 via nine inverters INV11 to INV19, and the output side is connected. The AND circuit AND1 is connected to the signal output terminal 2 (for example, Patent Document 1).

  In this edge detection circuit, since the output node N8 of the inverter INV19 is at the high level during the period when the signal input terminal 1 is at the low level, the signal output terminal 2 is at the low level. When the signal input terminal 1 rises to a high level in this state, the output node N8 of the inverter INV19 rises to a high level after the delay time by the nine-stage inverters INV11 to INV19 has elapsed, so that the signal output terminal 2 goes to a high level. Become. In this manner, an edge detection signal synchronized with the rising edge of the input signal is obtained from the signal output terminal 2 at the signal input terminal 1.

Japanese Patent Application No. 11-297097

  However, in the edge detection circuit shown in FIG. 5, as shown in FIG. 6, when a pulse P1 having a short pulse width is input, the node N5 changes from the high level to the low level and has dropped to the low level until just before that. The potential of N6 rises due to charging of the capacitor C2. When the potential of the node N6 reaches the threshold value Vth5 of the inverter INV5, the output side of the inverter INV5 is inverted to the low level. At this time, the pulse P1 of the signal input terminal 1 is already at the low level. Becomes a high level, and the power supply voltage VDD is applied to the capacitor C2, so that the potential of the node N6 rapidly rises to a potential obtained by adding the power supply voltage VDD to the charging voltage. Thereafter, the charge of the capacitor C2 is discharged via the resistor R3 and the power source.

  Then, if the next pulse P2 is input to the signal input terminal 1 before the potential of the node N6 falls to the ground potential GND, the potential of the node N5 changes to the low level again. And then charging to the capacitor C2 is resumed. As a result, the time until the potential of the node N6 reaches the threshold value Vth5 of the inverter INV5 is shorter than the previous time, and at this time, the pulse T5 width of the edge detection signal output from the signal output terminal 2 is the time when the previous pulse P1 is input. This becomes shorter than the pulse width T4 of the edge detection signal.

  The above phenomenon occurs because the interval T3 between the pulse P1 and the pulse P2 is short. In the case of the pulse P2, since the pulse width is long, the level when the potential of the node N6 starts to decrease is higher, and the interval until the next pulse input is, for example, the time T3 described above. , The pulse width of the obtained edge detection signal is even shorter than that when the pulse P2 is detected.

  As described above, in the edge detection circuit shown in FIG. 5, the pulse width of the edge detection signal to be output is not uniform depending on the interval and pulse width of the signal input to the signal input terminal 1. However, there is a problem that it is difficult to use in a circuit that affects circuit operation. Further, as shown in FIG. 6A, when the voltage transition of the node N6 is slow, when noise is superimposed on this signal, the signal IN the vicinity of the threshold value Vth5 of the inverter INV5 causes a signal fluctuation of the inverter INV5. There is also a problem that a hazard appears on the output side and a plurality of pulses may be output as an edge detection signal.

  On the other hand, in the edge detection circuit shown in FIG. 7, when a pulse P1 having a pulse width shorter than the total delay time of the inverters INV11 to INV19 is input to the signal input terminal 1, an edge detection having the same pulse width as that pulse P1 is performed. A signal is output to the signal output terminal 2. When a pulse P2 having a pulse width longer than the total delay time of the inverters INV11 to INV19 is input, an edge detection signal having a pulse width corresponding to the total delay time is output to the signal output terminal. Output to 2.

  As described above, even in the edge detection circuit shown in FIG. 7, depending on the pulse width of the signal input to the signal input terminal 1, the pulse width of the edge detection signal to be output is not uniform, and the pulse width of the edge detection signal is the circuit. There is a problem that it is difficult to use in a circuit that affects the operation. Further, as shown in FIG. 8B, when the voltage transition of the node N8 is slow, when noise is superimposed on this signal, a signal fluctuation near the threshold value of the AND circuit AND1 causes the output side to change. There is also a problem that a hazard appears and a plurality of pulses may be output as the edge detection signal.

  An object of the present invention is that an edge detection signal having a constant pulse width can be obtained without being affected by the pulse width and timing of an input signal, and a plurality of edge detection signals are output for edge detection of one input signal. It is an object to provide an edge detection circuit that has wiped out the problem.

In order to achieve the above object, an edge detection circuit according to a first aspect of the present invention includes a D-type flip-flop with an initialization function that changes a potential of a first node to a low level when a rising edge of an input signal is detected; A first switch element that conducts between a second node and a power supply terminal when the potential of the first node is at a low level; and the second node and ground when the potential of the first node is at a high level. A second switching element that conducts between the first node, a first inverter having an input side connected to the second node and an output side connected to a third node, and an input side connected to the third node. And a capacitor connected between the second node and the fourth node, and the third node is at a low level. The D-type flip-flop is initialized, and an edge detection signal having a pulse width from when the potential of the first node becomes low level until the D-type flip-flop is initialized is output. It is characterized by doing so.
According to a second aspect of the present invention, in the edge detection circuit according to the first aspect, the first switch element is replaced with a switch element group in which a plurality of switch elements having different on-resistances are connected in parallel, and the selection means is used to One switch element in the switch element group is selected.
The invention according to claim 3 is the edge detection circuit according to claim 1, wherein a first resistor is connected in series to the first switch element, and a second resistor is connected in series to the second switch element. When two or more input signals are intermittently input, the values of the first and second resistors are set according to the minimum interval.
According to a fourth aspect of the present invention, in the edge detection circuit according to the first, second, or third aspect, when the D-type flip-flop detects a falling edge of the input signal, the potential of the first node is changed to a low level. The D-type flip-flop is replaced.

  According to the first aspect of the present invention, a rising edge detection signal having a constant pulse width can be obtained regardless of the length of the pulse width of the input signal, and the second node to which the capacitor is connected is Since the positive feedback operation is performed, a plurality of pulses are not output for one edge detection. According to the invention of claim 2, by switching the first switch element to one having an on-resistance corresponding to the interval between a plurality of signals that are continuously input, the rising edges of those signals can be ensured. Can be detected. According to the invention of claim 3, by adjusting the values of the first resistor and the second resistor to values according to the interval between a plurality of signals that are continuously input, the rise of those signals Edges can be detected reliably. According to the fourth aspect of the present invention, the falling edge of the input signal can be detected in the same manner as described above.

1 is a circuit diagram of an edge detection circuit according to a first exemplary embodiment of the present invention. FIG. 2 is an operation waveform diagram of the edge detection circuit of FIG. 1. It is a circuit diagram of the edge detection circuit of the 2nd Example of this invention. It is a circuit diagram of the edge detection circuit of the 3rd Example of this invention. It is a circuit diagram of the edge detection circuit of the 1st prior art example. FIG. 6 is an operation waveform diagram of the edge detection circuit of FIG. 5. It is a circuit diagram of the edge detection circuit of the 2nd prior art example. FIG. 8 is an operation waveform diagram of the edge detection circuit of FIG. 7.

<First embodiment>
FIG. 1 shows an edge detection circuit according to a first embodiment of the present invention. In FIG. 1, FF1 is a D-type flip-flop, has an RB terminal (initialization terminal), a CK terminal connected to the signal input terminal 1, and a D terminal connected to the power supply terminal VDD. When the signal at the signal input terminal 1 rises from the low level to the high level, the flip-flop FF1 takes in the voltage VDD input to the D terminal and sets the Q terminal to the high level, but when the RB terminal becomes the low level, Initialize the pin to low level. The signal output terminal 2 and the input side of the inverter INV1 are connected to the Q terminal of the flip-flop FF1. The inverter INV2 including the PMOS transistor MP1 and the NMOS transistor MN1 is connected to the output side (node N1) of the inverter INV1. One end of the capacitor C1 and the input side of the inverter INV3 are connected to the output side (node N2) of the inverter INV2. The output side (node N3) of the inverter INV3 is connected to the input side of the inverter INV4 and the RB terminal of the flip-flop FF1. Further, the output side (node N4) of the inverter INV4 is connected to the other end of the capacitor C1. The nodes N1 to N4 are specific examples of the first to fourth nodes in the claims, the inverter INV3 is a specific example of the first inverter in the claims, and the inverter INV4 is a specific example of the second inverter in the claims. It is.

  Next, the operation will be described. In the standby state, the edge detection circuit of the present embodiment is such that the Q terminal of the flip-flop FF1 is low level, the output side (node N1) of the inverter INV1 is high level, the output side (node N2) of the inverter INV2 is low level, and the inverter INV3 The output side (node N3) is at a high level, and the output side (node N4) of the inverter INV4 is at a low level. Therefore, both ends of the capacitor C1 are at a low level, and the charge is zero.

  At this time, when a high level pulse signal P1 or P2 as shown in IN of FIG. 2 is input to the signal input terminal 1, the Q terminal of the flip-flop FF1 becomes high level at the rising edge, and the signal output terminal 2 becomes high level. To do. Further, the output side (node N1) of the inverter INV1 becomes low level, the transistor MP1 of the inverter INV2 is turned on, the transistor MN1 is turned off, and charging of the capacitor C1 is started. This charging is performed using the capacitance of the capacitor C1 and the on-resistance of the transistor MN1 as a time constant.

  When the potential of the node N2 reaches the threshold value Vth3 of the inverter INV3 by charging the capacitor C1, the inverter INV3 is inverted and the output side (node N3) is set to the low level. As a result, the output side (node N4) of the inverter INV4 becomes high level, so that the potential of the node N2 is raised to a voltage (= VDD + Vth3) equal to or higher than the power supply voltage VDD. At the same time, the flip-flop FF1 is initialized and the signal output terminal 2 becomes low level. Therefore, the output side (node N1) of the inverter INV1 becomes high level, the transistor MP1 of the inverter INV2 is turned off, the transistor MN1 is turned on, and the discharge of the charge of the capacitor C1 starts via the transistor MN1.

  When the potential of the node N2 falls below the threshold value Vth3 of the inverter INV3 due to the discharge of the capacitor C1, the inverter INV3 returns to bring the output side (node N3) to the high level. Thereby, the initialization of the flip-flop FF1 is released. Further, since the output side (node N4) of the inverter INV4 is at the low level, the potential at the node N2 is lowered to the GND level or less at once, and then returns to the GND level.

  Thus, the pulse width T1 of the edge detection signal obtained at the signal output terminal 2 is a time width from when the signal is input to the signal input terminal 1 until the potential of the node N2 reaches the threshold value Vth3 of the inverter INV3. The pulse width T1 is determined by the on-resistance of the transistor MP1 and the capacitance of the capacitor C1. The pulse width T2 of the signal at the node N3 is a time width from when the potential at the node N1 becomes high level until the potential at the node N2 falls below the threshold value Vth3 of the inverter INV3. This pulse width T2 is determined by the ON resistance of the transistor MN1 of the inverter INV3 and the capacitance of the capacitor C1. The pulse widths T1 and T2 are normally set to satisfy T2 <T1 by appropriately setting the ON resistances (size ratio W / L) of the transistors MP1 and MN1.

  As described above, according to the present embodiment, as shown in FIG. 2, an edge detection signal having a constant pulse width T1 is generated regardless of whether a pulse signal P1 having a short pulse width or a pulse signal P2 having a long pulse width is input. It can be obtained from the signal output terminal 2. The pulse interval T3 between the pulse signals P1 and P2 may be longer than the sum of the pulse width T1 of the edge detection signal and the pulse width T2 of the initialization signal appearing at the node N3 ((T1 + T2) <T3). Also, once the potential of the node N2 reaches the threshold value Vth3 of the inverter INV3, it is raised by the inverter INV4, and once it falls below the threshold value Vth3 of the inverter INV3, it is lowered by the inverter INV4. Even if the noise is mixed, it will not be affected. In the worst case, even if a large noise is superimposed on the capacitor C1 and a hazard appears in the output of the inverter INV3, only the noise appears in the initialization signal, and a plurality of edge detection signals appear at the signal output terminal 2. There is nothing.

<Second embodiment>
FIG. 3 shows an edge detection circuit according to the second embodiment of the present invention. In this embodiment, the PMOS transistor MP1 of the inverter INV2 is replaced with three PMOS transistors MP11, MP12, and MP13 having different size ratios (W / L), and these transistors MP11, MP12, and MP13 are used for switching in series. The PMOS transistors MP21, MP22, and MP23 are connected, and one of the transistors MP21, MP22, and MP23 is turned on by the selection circuit 3.

  According to the present embodiment, the charging time constant of the node N2, that is, the pulse width T1 of the edge detection signal can be switched, so that the input signal to be edge-detected depends on the circuit using the edge detection signal. The pulse width T1 may be selected according to the pulse interval (frequency, etc.).

<Third embodiment>
FIG. 4 shows an edge detection circuit according to a third embodiment of the present invention. In this embodiment, resistors R1 and R2 are connected in series to the PMOS transistor MP1 and NMOS transistor MN1 of the inverter INV2, respectively, and the values of the resistors R1 and R2 are set as appropriate, whereby the charging time constant and discharge for the capacitor C1 are set. The time constant is appropriately set so that the pulse width T1 of the edge detection signal and the pulse width T2 of the initialization signal can be adjusted. This embodiment is useful when setting a resistance higher than the ON resistance that can be set by the size ratio (W / L) of the transistors MP1 and MN1.

<Other examples>
1, 3, and 4, the inverter INV1 is used. However, if the signal at the inverted Q terminal of the flip-flop FF1 is extracted to the node N1, the inverter INV1 becomes unnecessary. . Further, if the flip-flop FF1 is replaced with a type that detects the falling edge of the signal input to the CK terminal, the edge detection signal synchronized with the falling edge of the signal input to the signal input terminal 1 by the same operation. Can be taken out from the signal output terminal 2.

Claims (4)

  A D-type flip-flop with an initialization function for changing the potential of the first node to a low level when a rising edge of the input signal is detected; and a second node and a power supply terminal when the potential of the first node is at a low level. A first switch element that conducts between the second switch element, a second switch element that conducts between the second node and the ground when the potential of the first node is at a high level, and an input to the second node A first inverter having a side connected to an output side connected to a third node, a second inverter having an input side connected to the third node and an output side connected to a fourth node, and the second node And a capacitor connected between the fourth node, the D-type flip-flop is initialized when the third node goes to a low level, and the first node Edge detection circuit potential of, wherein said D-type flip-flop after becoming low level and so the edge detection signal having a pulse width of up to initialize is output. The edge detection circuit according to claim 1,
The first switch element is replaced with a switch element group in which a plurality of switch elements having different on-resistances are connected in parallel, and one of the switch element groups is selected by the selection means. A feature edge detection circuit. The edge detection circuit according to claim 1,
A first resistor is connected in series to the first switch element, and a second resistor is connected in series to the second switch element. When the input signal is intermittently input two or more, according to the minimum interval An edge detection circuit in which values of the first and second resistors are set. In the edge detection circuit according to claim 1, 2, or 3,
An edge detection circuit, wherein the D-type flip-flop is replaced with a D-type flip-flop that changes the potential of the first node to a low level when the falling edge of the input signal is detected.

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