JP2624654B2 - Power-on reset circuit - Google Patents

Description

The present invention relates to a power-on reset circuit that generates a reset signal for a microprocessor and peripheral circuits when power is turned on.

(Prior Art) FIG. 4 shows a power-on reset circuit in a conventional microprocessor system.

In FIG. 4 (a), when the power supply voltage rises as shown in FIG. 5 (a) by turning on the power supply, this power supply voltage is applied to the capacitor 2 via the resistor 1, whereby the charging voltage of the capacitor 2 becomes As shown in FIG.
In accordance with a time constant determined by the resistance value of the capacitor 2 and the capacitance of the capacitor 2. The charging voltage of the capacitor 2 is applied to the hysteresis circuit 4.

The hysteresis circuit 4 has a low-level transposition voltage of 3.
78V, the high-level transposition voltage is set to 4.00V. When the input voltage rises to 4.00V, the output changes from low level (hereinafter, referred to as "L") to high level (hereinafter, referred to as "H"). When the input voltage falls to 3.78 V, the output changes from “H” to “L”. Therefore, when the power is turned on, the hysteresis circuit 4 is kept at "L" for a predetermined time (FIG. 5C).
Is output.

This reset signal is sent to the microprocessor and the peripheral circuit 5.

By the way, in the circuit shown in FIG. 4 (a), when the power supply is cut off, the capacitor 2 is discharged via the resistor 1 with the same time constant as that at the time of charging. There is a drawback that the signal does not go to "L" and no reset signal is generated. The circuit shown in FIG. 4 (b) eliminates the above-mentioned disadvantages. In this circuit, when the power is turned off, the capacitor 2 is discharged instantaneously via the diode 3. For this reason, "L" for a predetermined time even when the power is
Can be generated for the microprocessor and the peripheral circuit 5.

(Problems to be Solved by the Invention) In the above-mentioned conventional power-on reset circuit, the reset period by the reset signal is determined by the resistance value of the resistor 1 which is a discrete component and the capacitance of the capacitor 2, and therefore has a sufficient accuracy. Therefore, there is a problem that it is difficult to set the reset period. Also,
Considering the case where the reset period is changed, a configuration in which a plurality of resistors 1 or capacitors 2 are provided and these are switched by a strap, or a configuration in which the resistance 1 or the capacitor 2 is variable is considered, but the former causes an increase in discrete components. Therefore, the latter requires manual adjustment and has a problem in terms of time and accuracy.

Accordingly, an object of the present invention is to provide a power-on reset circuit having improved reset period accuracy and variability.

[Configuration of the invention]

(Means for Solving the Problems) According to the present invention, a power-on reset circuit for generating a reset signal to a microprocessor system when power is turned on has a threshold level for detecting a rise or fall of a power supply voltage. Power supply voltage detection means for detecting a power supply voltage, signal control means for generating and canceling generation of a clear signal in accordance with the detection result of the power supply voltage, signal generation maintaining means for maintaining generation of a clear signal when power is turned on,
Variable setting means capable of changing and setting the cycle of the clock pulse, and counting means for measuring the clock pulse when the generation of the clear signal is canceled by the signal control means and generating a reset signal when the count value reaches a predetermined value. And characterized in that:

(Operation) According to the present invention, a power supply voltage is detected based on a threshold level for detecting a rise or fall of the power supply voltage, and the signal control means generates and cancels generation of a clear signal in accordance with the detection result. In particular, the signal generation maintaining means can maintain the generation of the clear signal when the power is not turned on.

When the generation of the clear signal is canceled, a clock pulse is counted, and a reset signal is generated when the counted value reaches a predetermined value. The period of generation of the reset signal can be set by changing the cycle of the clock pulse. The cycle can be arbitrarily changed by the variable setting means.

(Embodiment) FIG. 1 shows an embodiment of the power-on reset circuit of the present invention.

The hysteresis circuit 100 has a low-level transposition voltage that transits from “H” to “L” and a high-level transposition voltage that transposes from “L” to “H”. For example, the low-level transposition voltage is
3.78V, high level transposition voltage is set to 4.00V. That is, when the input voltage rises, the output changes from "L" to "H" when the input voltage rises to 4.00V, and when the input voltage falls, the output drops to 3.78V and the output goes "H"
From “L” to “L”.

First, before the power is turned on, the output of the hysteresis circuit 100 is “L”, and this “L” signal is input to the clear input of the shift register 300. This allows the shift register 300
Has been cleared.

Next, when the power is turned on, the input voltage becomes 4.
When the voltage rises to 00V, the output from the hysteresis circuit 100 changes from “L” to “H”, whereby the shift register 300
Is cleared. The shift register 300 receives the frequency-divided clock pulse from the frequency divider circuit 200 at the clock input, and the data of “H” is input to the serial input, and is input to the serial input when the clear state is released. The "H" data is sequentially shifted in synchronization with the frequency-divided clock from the frequency-dividing circuit 200. The shift register 300 is configured such that a signal corresponding to the eighth stage of the parallel output is applied to the microprocessor and the peripheral circuit 400 as a reset signal.
The output of the eighth stage of 0 is at a low level until the data of “H” is shifted to the eighth stage, and this signal is applied to the microprocessor and the peripheral circuit 400 as a reset signal. Here, the period during which the output of the eighth stage of the shift register 300 is “L”, that is, the period during which the reset signal is generated, is the frequency of the frequency-divided clock pulse from the frequency dividing circuit 200 applied to the clock input of the shift register 300, that is, It can be set arbitrarily according to the set dividing ratio of the dividing circuit 200.

FIG. 2 shows a detailed circuit diagram of the embodiment shown in FIG. In FIG. 2, resistors 11, 12, and 1
3. The circuit including the voltage detecting circuit 14, the resistor 15, the inverter 16, and the battery 17 corresponds to the hysteresis circuit 100 in FIG. 1, and the circuit including the counters 20, 21, and the strap 22 corresponds to the frequency dividing circuit 200 in FIG. Correspondingly, the shift register 18 corresponds to the shift register 300 of FIG.

The voltage detection circuit 14 can operate from 1.8 V to 30 V, and the low-level transposition voltage is 3.78 V and the high-level transposition voltage is 4.00 V
Is set to

The inverter 16 is supplied with power from a battery 17, and its output is fixed to "L" by a pull-up resistor 15 when the power is off, and the shift register 18 is in a clear state. Each of the shift register 18 and the counters 20 and 21 is composed of a CMOS IC. As the battery 17, a battery for memory backup of the microprocessor and the peripheral circuit 400 can be used.

First, the power is turned on, and the input voltage rises as shown in FIG.
When the voltage reaches V, the output of the voltage detection circuit 14, that is, A in FIG.
The potential at the point changes from "H" to "L" as shown in FIG. 3 (b), and the output of the voltage detection circuit 14 is input to the inverter 16. As a result, the output of the inverter 16, that is, the potential at the point B in FIG. 2 changes from "L" to "H" as shown in FIG. 3 (c).

The output of the inverter 16 is input to the clear input ▼ of the shift register 18. Therefore, the reset state of the shift register 18 is released in synchronization with the timing when the output of the inverter 16 changes from “L” to “H”. The shift register 18 divides the clock pulse applied to the clock input terminal 19 from the counter 20, the counter 21 and the clock switching strap 22 to the clock input CK by a predetermined division ratio as shown in FIG. A divided clock pulse is input, and data of “H” is input to serial inputs A and B.

Here the counter 20 operates at the falling edge of the clock pulse input to a clock input terminal 19, half the frequency f of the clock pulses from the output Q ₁₂ of the counter 20 ^12-divided by the frequency f ₁ = f / 2 ¹² divided clock pulses are output. A clock input CK of the counter 21 frequency-divided clock pulse of frequency f ₁ is being counter 20 cascaded
Is input, the counter 21 frequency f ₂ = f _1/2 a further 1/2 ^12-divided clock pulse of the frequency f ₁ from the output Q ₁₂ of the falling operation and counter 21 of the clock pulse f ₁
^Twelve divided clock pulses are output. Thus divided clock pulse output from the output Q12 of the final counter 21, the frequency-divided clock pulse of frequency f ₂ = f / ₂ ²⁴ was 1/2 frequency ²⁴ binary clock pulses frequency f.

In this embodiment, the clock switching strap 22
From the counter 21, the frequency f _2n = f / 2 ^{12 + n} (where n =
1, 2,... 12) can be output.

The shift register 18 sequentially shifts “H” data applied to the serial inputs A and B in synchronization with the divided clock pulse from the counter 21 input to the clock input CK. The output signal of the eighth stage of the shift register 18 is applied to the microprocessor and the peripheral circuit 400 as a reset signal.

That is, the shift register 18 sends a reset signal that goes low until the “H” level data reaches the eighth stage to the microprocessor and the peripheral circuit 400. The generation period of the reset signal can be arbitrarily set by switching the clock switching strap 22. In the above embodiment, the frequency dividing circuit has a configuration in which the frequency dividing ratio is switched by switching the clock switching strap 22. However, the present invention is not limited to this. can do.

〔The invention's effect〕

As described above, according to the present invention, the reset period of the reset signal can be set with high accuracy, and the reset period can be easily varied.

In particular, according to the present invention, the generation of noise at power-on can be prevented to maintain the generation of a clear signal when power is not turned on, so that the counting means can operate normally and the peripheral elements can operate due to the power supply voltage. After that, the predetermined value related to the counting of the clock pulses by the counting means can be appropriately set so that the reset signal corresponding to the release of the clear signal can be generated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a power-on reset circuit of the present invention, FIG. 2 is a detailed circuit diagram of the embodiment shown in FIG. 1, and FIG. 3 is a circuit diagram shown in FIG. FIG. 4 is a circuit diagram showing a conventional power-on reset circuit, and FIG. 5 is a timing chart for explaining the operation of the circuit shown in FIG. 1 ... resistance, 2 ... capacitor, 3 ... diode, 4
... hysteresis circuit, 5 ... microprocessor and peripheral circuit, 11 ... resistor, 12 ... resistor, 13 ... resistor, 14 ...
... voltage detection circuit, 15 ... resistor, 16 ... inverter, 17 ...
... Battery, 18 ... Shift register, 19 ... Clock input terminal, 20 ... Counter, 21 ... Counter, 22 ... Clock switching strap, 100 ... Hysteresis circuit, 200
… Frequency divider circuit, 300 shift register, 400 microprocessor and peripheral circuit.

Claims (4)

(57) [Claims] 1. A power-on reset circuit for generating a reset signal to a microprocessor system when power is turned on, a power-supply voltage detecting means having a threshold level for detecting a rise or fall of the power supply voltage and detecting the power supply voltage. A signal control means for generating and releasing the clear signal in accordance with the detection result of the power supply voltage; a signal generation maintaining means for maintaining the generation of the clear signal when the power is turned on; and a cycle of the clock pulse can be changed and set. Variable setting means, and counting means for measuring the clock pulse when the generation of the clear signal is canceled by the signal control means and generating the reset signal when the count value reaches a predetermined value. A power-on reset circuit. 2. The power-on reset circuit according to claim 1, wherein said counting means comprises a shift register to which a clock pulse is applied as a shift pulse and generates a reset signal from a predetermined stage. 3. The power supply voltage detecting means includes a first threshold level for detecting a rise in power supply voltage due to power-on and a second threshold level for detecting a fall in power supply voltage due to power-off. 2. The power-on reset circuit according to claim 1, further comprising a hysteresis circuit for detecting a power supply voltage separately. 4. The power-on reset circuit according to claim 1, wherein said variable setting means comprises a variable frequency dividing circuit for dividing a predetermined clock pulse.