JP2844625B2 - Timer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a general-purpose digital circuit, which is started by a pulse input from the outside and outputs a signal of a certain level to the outside only for a certain period of time from the start. Circuit.

[Conventional technology]

Conventionally, as this type of timer circuit, a circuit in which a resistor 12 and a capacitor 13 are connected to a monostable multivibrator 11, as shown in FIG. In this circuit, as in the time chart of FIG. (B), the resistance value R of the resistor 12 to the timer set S _S, only timer output T ₀ between constant T = CR time determined by the capacitance C of the capacitor 13 Can be driven.

In addition, as shown in FIG.
Flip-flop 22 to the timer output T ₀ to the driving state S _S
Against the provided counter 21 outputs a timer set signal S _R, a clock CK generated by the clock generator 23 using a crystal oscillator 24 is counted by a counter 21 based on the counter data D _C, only between the count A circuit for operating the flip-flop 22 has also been proposed. In this circuit, as shown in FIG. (B), is output timer output T ₀ by the timer set signal S _S, the timer output T ₀ when the timer set signal S _R to complete the counting of the counter 21 is output Can be stopped.

[Problems to be solved by the invention]

In the above-described conventional timer circuit, the configuration is divided into a semiconductor unit including a transistor and a diode and a passive element unit including a resistor, a capacitor, and a crystal oscillator, and the semiconductor unit can be easily integrated by IC integration technology. In many cases, passive elements are externally mounted on these semiconductor parts, so that the mounting area increases, which hinders improvement in mounting density and miniaturization of the device.

For this reason, it is possible to combine passive elements together with semiconductor elements in a single IC package by using hybrid IC technology, but the manufacturing method becomes more complicated than monolithic ICs consisting only of semiconductor elements. is there.

Also, when the crystal unit is mounted on a printed circuit board,
There is also a problem that an output signal pattern from the crystal unit and the oscillator affects other signal patterns as noise.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a timer circuit capable of improving the mounting density and reducing the size of the device.

[Means for solving the problem]

A timer circuit according to the present invention includes a ring oscillator having an odd number of inverters and oscillating a clock, and starts counting a clock from the ring oscillator by an external timer set signal. A first counter to output, a flip-flop for setting a timer output by the timer set signal and resetting a timer output by a timer reset signal from the first counter, and a clock from the ring oscillator to an external reference While the signal is being input, counting is performed, and the counted value is used as the first value.
And a second counter that outputs a predetermined number of count values to the above counter.

[Action]

In the configuration described above, the ring oscillator, counter, and flip-flop can all be configured as monolithic ICs,
Eliminates the need for external components and achieves a simplified configuration.

Further, according to the present invention, by providing the second counter that counts based on the reference signal, while the reference signal is being input, the clock from the ring oscillator is first counted by the value actually counted by the second counter. , It is possible to set the timer output time with higher accuracy without depending on the oscillation frequency of the ring oscillator.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1A is a circuit diagram of a reference example of the present invention. This timer circuit includes a counter 1, a flip-flop 2, and a ring oscillator 3.

Counter 1 is activated by a timer set signal S _S, counted n times based on the clock CK the set counter data D _C supplied from the ring oscillator 3, the timer set for the flip-flop 2 when counting and outputs a signal S _R.

Counter data D _C is composed of m bits, to set the number of times (n) to count. In this case, the counter data
D _C is a method to keep the circuit as a fixed value, it can be either a method of setting from the outside.

Flip-flop 2 is the timer output T ₀ to the operating state when the timer set signal S _S is input, the timer output T ₀ in the non-operation state by the timer set signal S _R from the counter 2.

The ring oscillator 3 has k (k is an odd number) inverters
It is composed of 3 _{l to} 3 _k and outputs a clock CK and outputs it to the counter 1. Here, assuming that the average propagation delay time of each of the inverters 3 _{l to} 3 _k is td, the oscillation frequency f of the ring oscillator 3 is given by f = 1 / 2k · td.

Therefore, according to this configuration, as shown in the time chart Fig. 1 (b), the flip-flop 2 by a timer set signal S _S is a timer output T ₀ and the operation state. At the same time, the counter 1 starts counting the clock CK from the ring oscillator 3. Needless to say this count number is the number that is set by the count data D _C. Then, outputs a timer set signal T _R to the flip-flop 2 at the time when the required number of counts have been completed, the timer output T ₀ inoperative.

As a result, the timer set signal from the timer set input T _S
Timer operation by the timer output during T _R is realized. This timer time T is given by T = 2k · td · n.

In this circuit, the counter 1 is when the clock CK and during the l Count (1 <l <n), if entered timer set signal S _S again is capable retrigger.

FIG. 2A is a circuit diagram of the first embodiment of the present invention.
Here, a counter 4 as a second counter is added to the circuit of FIG. Counter 4 as the second counter measures the time of the reference signal R _REF timer by using a clock CK, and configured to output the counter data D _C corresponding to the time the counter 1 .

In addition the reference signal R _REF to the AND circuit 5 through an inverter 6, and configured to control the input of the timer set signal S _S by the AND circuit 5. However, the reference signal S _REF needs to be sufficiently longer than the clock cycle.

According to this configuration, the timer set signal S _S is input to the counter 1 and the flip-flop 2 only when the reference signal R _REF is not input. And when the device starts,
Alternatively, the reference signal R _REF is input to the counter 4 when changing the timer value. Counter 4 the input time of the reference signal R _REF determined by performing counting of the clock CK, is provided to the counter 1 as the counter data D _C.

Therefore, the output time of the timer circuit is obtained for the same number of clocks as the reference input time, and the ring oscillator 3
Does not depend on the oscillation frequency of the inverters, even if the propagation delay time of each of the inverters 3 _{1 to} 3 _k varies, an accurate timer output T ₀ can be obtained as compared with the reference example.

〔The invention's effect〕

As described above, according to the present invention, a timer circuit can be configured only with a semiconductor element without using a passive element such as a resistor, a capacitor, and a crystal oscillator which are conventionally required. It can be stored in a package. This makes it possible to reduce the size of the substrate and the device as compared with a case where a passive element is externally provided, and to simplify the manufacturing process as compared with a case where a hybrid IC is used.

Furthermore, since there is no need to supply a clock from outside,
There is no need to lay a clock signal pattern that easily gives noise to other signal patterns, and the reliability of the device can be improved.

After the reference is set, the same timer output time as the reference input time can be accurately obtained.

[Brief description of the drawings]

FIG. 1 shows a reference example of the present invention. FIG. 1 (a) is a circuit diagram, FIG. 1 (b) is a timing chart thereof, and FIG. 2 shows a first embodiment of the present invention. 3A shows a circuit diagram, FIG. 3B shows a timing chart thereof, FIG. 3 shows an example of a conventional timer circuit, FIG. 3A shows a circuit diagram, and FIG. FIG. 4 shows another example of the conventional timer circuit, and FIG.
2 is a circuit diagram, and FIG. 2B is a timing chart thereof. 1 ... Counter, 2 ... Flip-flop, 3 ... Ring oscillator, 4 ... Counter, 5 ... And circuit, 6
…… Inverter, 11 …… Monostable multivibrator, 12
…… Resistance, 13 …… Capacitor, 21 …… Counter, 22 ……
Flip-flop, 23 ... Clock generator, 24 ...
…Crystal oscillator.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 17/28

Claims (1)

(57) [Claims] A ring oscillator having an odd number of inverters and oscillating a clock, a clock from the ring oscillator is started by an external timer set signal, and a timer reset signal is output after a predetermined number of counts. A first counter, a flip-flop that sets a timer output by the timer set signal, and resets a timer output by a timer reset signal from the first counter; A second counter that counts while being input and outputs the counted value as a predetermined number of count values to the first counter.