JPH02180425A - Timer circuit - Google Patents

Abstract

PURPOSE:To house the timer circuit in one IC package by the integration technique of a monolithic IC and to miniaturize a substrate and the device by composing the timer circuit only of a semiconductor element without using a passive element such as a resistance, a capacitor, and a crystal resonator. CONSTITUTION:The timer circuit is composed of a counter 1, a flip-flop 2, and a ring oscillator 3. The flip-flop 2 makes a timer output TO into an operating state by a timer set signal SS. Simultaneously with this, the counter 1 starts counting a clock CK from the ring oscillator 3. It goes without saying that this counted number is a number to be set by count data DC. Further, at a point where the counting of the required number of clocks completes, a timer reset signal TR is outputted to the flip-flop 2, and the timer output TO is made into a non-operation state. As the result, a timer operation by timer outputs from a timer set input TS up to the timer reset signal TR can be realized. The timer time T can be given with T=2k.td.n.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention is a general-purpose digital circuit that uses a timer that is activated by an external pulse and outputs a signal at a certain level to the outside for a certain period of time from the time of activation. Regarding circuits.

[Conventional technology]

Conventionally, as a timer circuit of this type, one in which a resistor 12 and a capacitor 13 are connected to a monostable multipipe lake 11 has been proposed, as shown in FIG. 3(a). In this circuit, as shown in the time chart of FIG. 2(b), the timer output T is generated only during the time constant T=CR determined by the resistance value R of the resistor 12 and the capacitance C of the capacitor 13 with respect to the timer set signal Ss.

can be driven.

Further, as shown in FIG. 4(a), a counter 21 is provided which outputs a timer reset signal S□ to a flip-flop 22 which drives the timer output T0 with the timer reset signal S, and A circuit has also been proposed in which a clock CK generated by a clock generator 23 using a clock generator 24 is counted by a counter 21 based on counter data Dc, and a flip-flop 22 is operated only during this counting period. In this circuit, as shown in FIG. 2(b), timer output T0 is output with timer set signal S, and counter 2
The timer output T0 can be stopped when the count of 1 is completed and the timer reset signal S+t is output.

[Problem to be solved by the invention]

In the conventional timer circuit mentioned above, a transistor.

The structure is divided into a semiconductor part made of diodes, etc., and a passive element part made of resistors, capacitors, and crystal resonators.The semiconductor part can be easily integrated using IC integration technology, but passive elements cannot be attached externally to these semiconductor parts. In many cases, the mounting area is increased, which becomes an obstacle to improving the mounting density and downsizing the device.

For this reason, it is possible to combine passive elements and semiconductor elements into one IC package using hybrid IC technology, but this poses the problem that the manufacturing method is more complicated than that of monolithic ICs that consist only of semiconductor elements. be.

Furthermore, when a crystal resonator is mounted on a printed circuit board, there is a problem in that output signal patterns from the crystal resonator and oscillator affect other signal patterns as noise.

SUMMARY OF THE INVENTION An object of the present invention is to provide a timer circuit that can improve packaging density and reduce the size of the device.

[Means to solve the problem]

The timer circuit of the present invention includes a ring oscillator that includes an odd number of inverters and oscillates clocks, and a clock from this ring oscillator that starts counting by an external timer set signal, and after counting a predetermined number of clocks, a timer reset signal is sent. and a flip-flop that sets the timer output by the timer set signal and resets the timer output by the timer reset signal from the counter.

[Effect]

In the above configuration, the ring oscillator, counter, and flip-flop can all be configured with a monolithic IC,
External attachment eliminates the need for parts and simplifies the configuration.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a circuit diagram of a first embodiment of the present invention. This timer circuit has counters 1. flip flop 2. It is composed of ring oscillator 3.

The counter 1 is activated by a timer set signal s3, counts the clock CK supplied from the ring oscillator 3 once based on the set counter data DC, and when the counter 1 counts, sends a timer reset signal SR to the flip-flop 2. Output.

Counter data Dc is composed of m bits and allows the number of times (n) to be counted to be set. In this case, the counter data D can be set either by configuring the circuit as a fixed value or by setting it externally.

The flip-flop 2 turns the timer output T0 into an active state when the timer set signal S is input, and turns the timer output T0 into an inactive state by the timer reset signal SR from the counter 2.

The ring oscillator 3 has two (k is an odd number) inverters 3
．． 3k and outputs a clock CK, which is output to the counter 1. Here, each inverter 3. ~3.
When the average propagation delay time of is td, the oscillation frequency f of the ring oscillator 3 is given by f=1/2 -Cd.

Therefore, according to this configuration, as shown in the time chart of FIG. 1(b), the flip-flop 2 sets the timer output T0 to the operating state by the timer set signal Ss.

At the same time, the counter 1 starts counting the clock CK from the ring oscillator 3. This count number is count data D.

Needless to say, this is the number set by . Then, when the required number of counts is completed, a timer reset signal TR is output to the flip-flop 2, and the timer output T is output. is inactive.

As a result, a timer operation based on the timer output between the timer set manually and the timer reset signal Ti0 is realized. This timer time T is given by -td-n where T=2.

In this circuit, retriggering is possible if the timer set signal S is input again when the counter 1 counts β clocks CK (1<z<n).

FIG. 2(a) is a circuit diagram of a second embodiment of the present invention. Here, a counter 4 is added to the circuit shown in FIG. 1(a). This counter 1 is configured to measure the time of the timer reference signal R□ using the clock CK, and output counter data Dc corresponding to this time to the counter 1.

Further, the reference signal RREF is applied to the AND circuit 5 through the inverter 6, and the AND circuit 5 is configured to control the input of the timer set signal S. However, the reference signal SIIEF needs to be sufficiently longer than the clock cycle.

According to this configuration, only when the timer set signal S and the reference signal RREF are not input, the counter 1. Human power is applied to flip-flop 2. Then, when starting up the device or changing the timer value, a reference signal S■ is sent to the counter 4.

Enter. The counter 4 measures the input time of the reference signal RREF by counting the clock CK, and provides this to the counter 1 as counter data Dc.

Therefore, the output time of the timer circuit is obtained by the same number of clocks as the reference input time, and does not depend on the oscillation frequency of the ring oscillator 3, so the inverter 3. Even if there are variations in the respective propagation delay times between 3 and 3, a more accurate timer output T0 can be obtained than in the first embodiment.

〔Effect of the invention〕

As explained above, the present invention provides a resistance that is conventionally required.
Since the timer circuit can be constructed using only semiconductor elements without using passive elements such as capacitors and crystal oscillators, it can be accommodated in one IC package using monolithic IC integration technology. This allows for miniaturization of the board and device compared to the case where a passive element is externally attached, and also simplifies the manufacturing process compared to the case of using a hybrid IC.

Furthermore, since there is no need to supply a clock from the outside, there is no need to provide a clock signal pattern that tends to cause noise to other signal patterns, and the reliability of the device can be improved.

Furthermore, after setting the reference, it is possible to accurately obtain the timer output time that is the same as the reference input time.

[Brief explanation of the drawing]

FIG. 1 shows a first embodiment of the present invention, and FIG.
is a circuit diagram, FIG. 2(b) is a timing chart thereof, and FIG. 2 shows a second embodiment of the present invention, FIG. 2(a) is a circuit diagram, and FIG. , 3rd
The figure shows an example of a conventional timer circuit.
is a circuit diagram, FIG. 4(b) is a timing chart thereof, and FIG.
FIG. 1A is a circuit diagram, and FIG. 1B is a timing chart thereof. 1...Counter, 2...Flip-flop, 3...
・Ring oscillator, 4 6... Inverter, 12... Resistor, 22... Free generator, 2... Counter, 5... AND circuit, 11... Monostable multi-wire 13... Capacitor, 21... Coup flop,
23...Clock 4...Crystal oscillator. (a) (b) μmayo - J animals 55s Noima voice power 3 Figure 4 (a) (b) Yu O・, 2 C for 1 = J1 and sharp Kuitsuruka 1 go -1

Claims (1)

[Claims] 1. A ring oscillator that has an odd number of inverters and oscillates a clock; a counter that starts counting the clock from this ring oscillator in response to an external timer set signal, and outputs a timer reset signal after counting a predetermined number; A timer circuit comprising: a flip-flop that sets a timer output by the timer set signal and resets the timer output by a timer reset signal from the counter.