SU688993A1 - Pulse recurrence frequency divider with variable division factor - Google Patents

Description

the complementary input of the first element of the IS block of the installation.

The drawing shows a structural electrical circuit of a pulse frequency divider with a variable division factor.

It contains a counter of 1 pulses, blocks 2, 3 of fixation, elements of H-HE 4, 5, 6 of the installation unit, inverter 7 and block 8 of setting the code.

The device works as follows.

Counter 1 with a natural counting order has 10 states. Block 2 is triggered when counter 1 is in the fifth and tenth state, issuing a "Meander." Signal to the high decade. After filling the highest decade, it receives a signal with a logic zero level, which enables operation of block 3. Block 3 identifies the ninth state of the counter by the output signal of its fourth trigger (with a division factor of 10, the output of the first trigger of counter 1 is also supplied) and the input pulse, translating w, th counter 1 to the tenth state, passes to the output and sets the trigger of block 3 to the initial position.

The same impulse, the passage through the inverter 7 and the element IS-HE 5, does not install the second and third triggers of counter 1. Since the highest speed requirements are imposed on the first trigger of counter 1, it is set by the output signal of the fourth trigger of counter 1, pass This element does not transfer the first trigger of counter 1 to the opposite state, but saves the previous state of the trigger. Due to this, the minimum magnitude of the input signal period is equal to the response time of the triggers of counter 1, i.e. the device realizes the maximum speed of the elements included in it.

The installation of the first three triggers of counter 1 makes it possible to obtain eight division factors from 2 to 9. Division factors 1 and 10 are achieved with the help of additional signals arriving at the control inputs of the fourth

the trigger of counter 1 after filling the senior decade from block 8. With division factor 1, the additional signal is a signal with a constant level of logic zero; with division factor 10, the output signal of the first trigger of counter 1. With division factors 2-9 by these control inputs the fourth trigger of the counter 1 receives a signal with a constant

level of logical units.

The frequency divider following imulses with a variable division factor realizes the maximum speed of the / - / (- triggers included in it.

Claims (2)

Invention Formula A pulse frequency divider with a random dividing factor, containing an impulse counter on triggers, two fixing blocks, the first input of each of which is connected to the input bus, and the second inputs to the outputs of the counter of pulses, the code setting unit, the installation unit consisting of three elements NAND, the first inputs of which are connected to the code setting block, and the outputs to the installation inputs of the corresponding pulse counter triggers, the second inputs of the second and the third unit's IS-NOT unit is connected via an inverter to the output of the second fixation unit, characterized in that, in order to improve the reliability of the pulse frequency divider while maintaining its maximum speed, the output of the fourth trigger of the pulse counter is connected to the input of the first AND-NOT unit installation, the code setting unit is connected to the control inputs of the fourth trigger and to the first auxiliary input of the second fixation unit, the second auxiliary input of which is connected to the auxiliary input m first AND-NO ustanovkn block. Sources of information taken into account during the examination 1. USSR Author's Certificate No. 513508, cl. H OZK 23/00, 08.08.74. 2. USSR author's certificate No. 509999, cl. N OZK 23/00, 08.27.74.