SU790348A1 - Decimal counter - Google Patents

Description

(54) DECIMAL COUNTER

The invention relates to a pulse technique and can be used for counting and dividing signals in various (mainly decimal) digital computing and measuring devices implemented by means of an integrated technology in the basis of potentized logic elements. The tenth counter is known, the contents are four --RS-triggers and a control unit, the outputs of which are connected to the set and reset inputs of RS-flip-flops 11, the most decisive by technical essence to the proposed is the decimal counter, the four RS-flip-flops and the block Control 2 The disadvantage of these decade counters is their relatively low reliability. The purpose of the invention is to increase the number above the tenth counter. This goal is achieved by the fact that an additional control unit is inserted into a decimal counter containing four RS flip-flops and a control unit. Neither the first and the second decoders, the first output of the control unit is connected to the installation input of the first RS flip-flop and the first input of the first decoder, the first output of which is connected to the first input of the control unit, the second output is connected to the first reset input of the first RS-flip-flop, First input installation of the second RStrigger and the second input of the first decoder, the second output of which is connected to the second input of the control unit, the third output of which is connected to the second reset input of the first RStrigger, the reset input of the second Strigger and third input of the first decoder, the third output is connected to. the third input of the control unit, the fourth input of the first decoder is connected to the inverse output of the first RS flip-flop, the direct output of which is connected to the fifth and sixth inputs of the first di-diffractor, the seventh input of which is connected to the inverse output of the second RS-three epa, the direct output of which connected to the eighth input of the first decoder, the first output of the additional control unit is connected to the installation input of the third RS flip-flop and the first input of the second decoder, the first output of which is connected to the first input of the additional control unit ION. The second output of which is connected to the first reset input of the third RS trigger, the installation input of the fourth RS flip-flop and the second input of the second decoder, the second output of which is connected to the second input of an additional control unit, the third output of which is connected to the second input of the second RS flip-flop, the second reset input of the third RS flip-flop by the reset input of the fourth RS flip-flop and the third input of the second decoder, the third output of which is connected by the third input of an additional control unit, the fourth input of the second decryptor Pa is connected to the inverse output of the third RS flip-flop, the direct output of which is connected to the fifth and above. the second inputs of the second decoder, the seventh input of which is connected to the inverse output of the fourth RS flip-flop, my output of which is connected to the eighth input of the second decoder, the fourth, fifth and sixth inputs of the control unit connected to the input of the decimal counter, and the fourth output of the unit control is connected to the fourth and fifth inputs of the additional control unit, the sixth input and the fourth output of which are connected respectively to the input and output of the ten-meter counter. Each control unit contains the first, second and third elements OR NOT (INE) and the inverter, the output of the first element IL11-PE (AND-NO) is connected to the first output of the control unit and the inputs of the second and third elements OR-NOT (AND-NO) , the output of the second element ILINE (IS-NOT) is connected to the second output of the control unit and the inputs of the first and third element 1t OR-NOT (AND-NO), the output of the third element ILINE (AND-NO) is connected to the third output of the control unit, the inputs of the first and the second element OR-NOT (EH) and the input of the inverter, the output of which is connected to the fourth output control unit, the first and fourth inputs of the control unit are connected to the inputs of the first element OR NOT (AND-NOT), the second and fifth inputs of the control unit are connected to the inputs of the second element OR-NOT (AND-NOT), the third and sixth inputs the control unit is connected to the inputs of the third element YLI-NOT (AND-NOT). Each decoder contains an element OR-NOT (AND-NO) and the first and second elements AND-OR-NOT the first output of the decoder is connected to the output of the element OR-NOT (AND-NOT), the first and second inputs of which are connected to the first and fourth inputs of the decoder the second output of which is connected to the output of the first element AND-OR-NOT, the input OR and the first and second inputs. And which is connected respectively to the second, fifth and seventh inputs of the decoder, the third output of which is connected to the output of the second element II-ILIE; the OR input and the first and second inputs of AND are connected respectively to the third, sixth and eighth inputs of the decoder. The block diagram of the decimal counter is shown in the drawing. The decimal counter contains four RS-flip-flops 1,2,3 and 4, a control block 5, an additional control block 6, the first 7 and the second 8 decoders. The first output of control unit 5 is connected to the installation input of the first RS flip-flop 1 and the first input of the first decoder 7, the first output of which is connected to the first input of control unit 5, the second output of which is connected to the first reset input of the first RS-flip-flop 1, first input of the second installation RS trigger 2 and the second input of the first decoder 7, the second output of which is connected to the second input of control unit 5, the third output of which is connected to the second reset input of the first short-circuit trigger 1, the reset input of the second RS-trigger 2 and the third input decoder 7, the third output of which is connected to the third input of the control unit 5. The fourth input of the first decoder 7 is connected to the inverse output of the first RS flip-flop 1, the direct output of which is connected to the fifth and sixth inputs of the first decoder 7, the seventh input that is connected to the inverse output of the second RS-flip-flop 2, the direct output of which is connected to the eighth input of the first decoder 7. The first output of the additional control unit b is connected to the installation input of the third RS flip-flop 3 and the first input of the second decoder 8, the first output of which is connected to the first input of the additional control unit b, the second output which is connected to the first reset input of the third RS flip-flop 3, the installation input of the fourth RS flip-flop 4 and the second input of the second decoder 8, the second output of which is connected to the second input of the additional control unit 6, the third output of which is connected to the second input of the second RS-flip-flop setting 2, the second reset input of the third RS flip-flop 3, the reset input of the fourth RS flip-flop 4 and the third input of the second decoder 8, the third output of which is connected to the third input of the additional control unit b. The fourth input of the second decoder 8 is connected to the inverse output of the third KZ-flip-flop 3, the direct output of which is connected to the fifth and sixth inputs of the second decoder 8, the seventh input of which is connected to the inverse output of the fourth RStrigger 4, the forward output of which

connected to the eighth input of the second decoder 8. The fourth, fifth and sixth inputs of the control unit 5 are connected to the input 9 of the decade counter, and the fourth output of the control unit 5 is connected to the fourth and fifth inputs of the additional control unit 6, the sixth input and the fourth output of which connected to input 9 and output 10 of a decimal meter, respectively. Each block 5 and b of the control contains the first 11, second 12 and third 13 elements OR-NOT (AND-NO) and inverter 14. The output of the first element OR-NOT (AND-NO) 11 is connected to the first output of the control unit and the outputs of the second and the third 13 elements OR NOT (AND-NOT), the output of the second element OR NOT (AND-NO) 12 is connected to the second output of the control unit and the inputs of the first 11 and third 13 elements OR NOT (AND-NOT), the output of the third element OR NOT (AND-NOT) is connected to the third output of the control unit, the inputs of the first 11 and second 12 elements OR-NOT (AND-NO) and the input of the inverter 14, the output of which nen a fourth output of the control unit. The first and fourth inputs of the control unit are connected to the inputs of the first element OR NOT (AND-NO) 11, the second and fifth inputs of the control unit are connected to the inputs of the second element OR NOT (AND-NO) 12, the third and sixth inputs of the control unit are connected with the inputs of the third element OR-NOT (AND-NO) 13. Each decoder 7 and 8 contains the element OR-NOT (AND-NO) 15, the first 16 and the second 17 elements AND-OR-NO. The first output of the decoder is connected to the output of the OR-NOT (AND-NO) element 15, the first and second inputs of which are connected to the first and fourth inputs of the decoder, the second output of which is connected to the output of the first AND-OR-NOT 16 input, OR input and the first and the second inputs of AND are connected respectively to the second, fifth and seventh inputs of the decoder, the third output of which is connected to the output of the second element AND-OR-NOT 17, the input of OR and the first and second inputs of AND are connected to the third, sixth and eighth respectively decoder inputs

The grand counter operates as follows.

In the initial state at the input 9 there is a single logic signal (high level), and at the direct outputs of the RS-flip-flops 1,2,3 and 4

1100

Wherein

code present

the first three outputs of blocks 5 and 6 of the control are supported by zero logical signals (low level). On the fourth input of block 5 of control there is a single logical signal, which in turn supports zero logic signals on the first

three outputs of the control unit 6. In the taKOM initial state, the device remains until the arrival of the first counting pulse.

The appearance at input 9 of a zero logic signal (first pulse) results in a change in the state of control block 5 in accordance with the output signals of the decoder 7. The signals from the outputs of control block 5 are fed to the R inputs of RS flip-flops 1

o and 2, set them to zero, i.e. the code on the direct outputs of these triggers will be 00. At the fourth output of control block 5, a zero logic signal appears, allowing

5 a change in the state of the control unit 6, which sets the RS flip-flop 3 to a single logic state on the installation input. During the change of signals at the outputs of RS-flip-flops

The signals input to the inputs of the decoders 7 and 8 may vary at the outputs of these decoders. However, these short-term changes do not disrupt the operation of the device, since a single logical signal at the corresponding output of the control unit maintains the state of the other outputs of the control unit at a zero logic level and, moreover, does not allow the signal to change to

0 the output of the decoder, which could change the state of the control unit. After the end of the transient processes caused by the appearance of the first pulse, the code 0010 will be set on the direct outputs of the RS-flips. In this state, the device remains until the signal at input 9 changes from zero to one. The second pulse sets on the outputs of RS-flip-flops

0

Another (third)

1010

code

the counting pulse at input 9 sets the outputs of the RS-flip-flops in the same way as the ITO code described above, etc. After the ninth pulse, the code at the outputs of the RS flip-flops will be 0011,

5 The tenth pulse causes the appearance at the outputs of blocks 5 and 6 of the control of single logic signals, which set the RS-TriggerF in

1100

Wherein

code status

at output 10, an output pulse of the input frequency is formed, the tenth pulse, which coincides in phase with the tenth input pulse. This pulse can be used to start the higher decades of the counter as its size increases, and the appearance at the input 9 of a single logical signal of the device returns to the initial state.

Claims (2)

Invention Formula .one. A decanter counter containing four RS-trngers and a control unit is supplied so that, in order to increase reliability, an additional control unit and the first and second decoders are introduced into it, the first output of the control unit Unified with the installation input of the first RS trigger and the first input of the first decoder, the first output of which is connected to the first input of the control unit, the second output connected to the first reset reset of the first RS trigger, the first input of the installation of the second RS trigger, and the second input of the first decoder, second exit The hog is connected to the second input of the control unit, the third output of which is connected to the second reset input of the first RS flip-flop, the reset input of the second RS flip-flop and the third input of the first decoder, the third output of which is connected to the third input of the control unit, the fourth of the first decoder is connected to the inverse the output of the first RS-trigger, the direct output of which is connected to the fifth and sixth inputs of the first decoder, the seventh input of which is connected to the inverse output of the second RS - flip-flop, the direct output of which is connected to the eighth the input of the first decoder, the first output of the additional control unit is connected to the installation input of the third RS-flip-flop and the first input of the second decoder, the first output of which is connected to the first input of the additional control unit, the second output of which is connected to the first reset input of the third RS-flip-flop , the installation input of the fourth RS flip-flop and the second input of the second decoder, the second output of which is connected to the second input of the additional control unit, the third output of which is connected to the second input of the installation of the second R Trigger, the second reset input of a third of its RS flip-flop, the reset input of the fourth RS-flip-flop and the third input of the second decoder, the third output of which is connected to the third input of the additional control unit, the fourth input of the second decoder is connected to the third output of the third RS-trigger, my output is connected to the fifth and sixth inputs of the second decoder, the seventh input of which is connected to the inverse output of the fourth RS flip-flop, the direct output of which is connected to the eighth input of the second decoder, the fourth, fifth and fifth the inputs of the control unit are connected to the input of the decimal counter, and the fourth output of the control unit is connected to the fourth and fifth inputs of the additional control location, the sixth input and the fourth output of which are connected respectively to the input and output of the child counter. 2. The decimal counter according to claim 1, characterized in that each control unit contains the first and third elements OR-NOT (AND-NOT) and the inverter, the output of the first element OR-NOT (and-NOT) is connected with the first, output of the unit control and inputs of the second and third elements OR NOT (AND-NOT), the output of the second element OR-NOT (AND-NO) is connected to the second output of the control unit and the inputs of the first and third elements OR-NOT (AND-NOT), output the third element OR NOT (AND-NO) is connected to the third output of the control unit, the inputs of the first and second elements OR-NOT (AND-NO) and the input of the inverto Pa, the output of which is connected to the fourth output of the control unit, the first and fourth inputs of the control unit are connected to the inputs of the first element OR NOT (AND-NES), the second and fifth inputs of the control unit are connected to the inputs of the second element OR-IE (AND-NOT ), the third and sixth inputs of the control unit are connected to the inputs of the third element OR NOT (AND-NO). 3. The decimal counter according to claim 1, characterized in that each decoder contains an OR-NOT (AND-NOT) element and the first and second AND-OR-NOT elements, the first input of the decoder is connected to the output of the ILINE element (AND-NO ), the first and second inputs of which are connected to the first and fourth inputs of the decoder, the second output of which is connected to the output of the first AND-OR-NOT element, input OR and the first and second inputs AND of which are connected respectively to the second, fifth and seventh inputs the decryption of the ator, the third output of which is connected to the output of the second AND-OR-NOT element, the input AND And the first and second inputs of which are connected respectively and the third, sixth and eighth input of the decoder. Sources of information taken into account in the examination 1.Shurygin I.T., Novikov L.G.Daetic recalculators on hybrid integrated circuits, Instruments and control systems, 1976, 11, p. 44-45. 2. Design of electronic devices on integrated circuits. -Ed. S.Ya.Shatsa.I., Soviet Radio, 1976, p. 242, fig. 5.52 (prototype)