JPS6130451B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable counter that has high-speed operating characteristics and is suitable for implementation as an integrated circuit.

A programmable counter is a frequency divider that can set the division value, and is a PLL (phase locked).
Widely used in loop) circuits, etc. Especially recently, many devices are constructed as large-scale integrated circuits (LSI).
Therefore, low power consumption and high-speed operation characteristics are required. The most widely used type is CMOS
It is LSI. However, CMOS/LSI also has various limitations in achieving high-speed operation characteristics. For example, a flip-flop that constitutes a counter has a large number of gates, which reduces its operating speed.

The configuration of the conventional programmable counter is
As shown in the figure. In the figure, 1 and 2 are one-tenth frequency divider circuits, and 3 is a D-type flip-flop. P ₁ , P ₂ , P ₄ , and P ₈ are preset input terminals corresponding to preset values 1, 2, 4, and 8, respectively. _P10 , _P20 , _P40 , _P80
are preset input terminals corresponding to preset values 10, 20, 40, and 80, respectively.

Since this circuit is a well-known circuit, its operation will be briefly explained. FIG _. 2 is a diagram of its operating waveforms, where a, b, c _, and d are the waveforms at points with corresponding symbols in _FIG . The waveforms of each output are shown. Clock signal a is applied to input IN. Now, if we take "4" as a representative example of an even number as the preset value, the output of frequency divider circuit 1 will be
_Q1 simply performs a binary operation as shown in Figure 2b. Furthermore, the output waveforms of the outputs Q ₂ , Q ₄ , and Q ₈ of the frequency dividing circuit 1 repeatedly count down from the preset value "4", as shown in FIG. Therefore, the output OUT becomes as shown in Fig. 2c. If the preset value is an odd value, a typical example being "5", the first stage circuit is inverted for each preset value, so the waveform of the output _Q1 of the frequency divider circuit 1 becomes as shown in Figure 2b', The output waveforms of the outputs Q ₂ , Q ₄ , and Q ₈ of the circuit 1 are as shown in Q ₂ ', Q ₄ ', and Q ₈ ' in Figure 2, and the countdown is repeated from the preset value "5", and the output OUT is It will look like Figure 2 c'.

The conventional example circuit shown in Fig. 1 is a presettable circuit.
The circuit is constructed by a combination of flip-flops, and with this construction, it is not possible to expect much improvement in operating speed. That is, when comparing the operating speeds of the presettable flip-flop shown in Fig. 3 and the binary flip-flop shown in Fig. 4, the operating speed of the presettable flip-flop shown in Fig.
When the structure and other conditions are equal, the former has a maximum of about 10 MHz, and the latter has a maximum of about 20 MHz. In FIG. 3, P is a preset terminal, PE is a preset enable terminal, and in FIGS. 3 and 4, φ and gate electrodes are supplied with a clock signal CK which is inverted with respect to each other.

The present invention focuses on improving the speed of a programmable counter using this binary flip-flop, and aims to provide a programmable counter that can obtain faster operating characteristics than conventional programmable counters.

The present invention is characterized by a structure using a binary flip-flop in the first stage. In other words, in a programmable counter that operates as a 1/N frequency divider, the first input stage is composed of a binary flip-flop, and the output of the binary flip-flop has a phase whose phase is inverted by the output signal of the programmable counter when the frequency division value is an odd number. It is characterized by a circuit configuration that is connected to the clock terminal of the next-stage presettable flip-flop through a control circuit.

Next, a more detailed explanation will be given using examples.

FIG. 5 is a circuit diagram of a device according to an embodiment of the present invention.

This embodiment circuit uses a high-speed binary counter that receives an input clock signal in front of a conventional presettable programmable counter, which is a one-fifth frequency divider circuit and a one-tenth frequency divider circuit, that is, a 1/50 frequency divider circuit. A high-speed 1/2 frequency divider circuit is provided, which is comprised of a flip-flop and a phase control circuit that inverts the output of the binary flip-flop according to the logic value of the least significant digit of the preset value.

In the figure, 11 is a one-fifth frequency dividing circuit, and 12 is a one-tenth frequency dividing circuit. 13 and 14 are binary flip-flops, 15 is a D-type flip-flop, and 16 is a NAND circuit. The input IN is
is applied to the clock input of binary flip-flop 13.
The output of 3 is passed through the NAND circuit 16 to the frequency divider circuit 1.
1 clock input. The output Q ₈ of this frequency dividing circuit 11 is the frequency dividing circuit 1
2 clock input. Frequency divider circuit 1
Preset inputs P ₂ , P ₄ and P ₈ of 1 correspond to preset values 2, 4 and 8, respectively. Preset input P ₁ corresponding to preset value 1
is provided to inhibit the clock input of binary flip-flop 14. This is a configuration for inhibiting the operation of the binary flip-flop 14 when the preset value is an odd number.

The outputs Q ₂ , Q ₄ of each frequency dividing circuit 11 and 12,
Q ₈ , Q ₁₀ , Q ₂₀ , Q ₄₀ , and Q ₈₀ are synthesized by a gate circuit as in the known circuit, and a D-type flip-flop 15 is operated by the clock signal of the input IN.
, and its output Q is led to the output OUT. Further, this output Q is given to the clock input of a binary flip-flop 14, and this output Q is configured to gate the output of the binary flip-flop 13 mentioned above with a NAND circuit 16.

In other words, this configuration replaces only the first stage that requires high-speed operation with a binary flip-flop, and uses the same structure as the conventional structure for the frequency divider circuits in the second and subsequent stages, thereby achieving high-speed operation that could not be achieved with circuits with conventional structures. It is an attempt to obtain.

Here, the frequency dividing circuits 11 and 12 perform 2/N frequency division when the least significant digit of the preset value N is "0", that is, N is an even number, and when the least significant digit of the preset value N is "1", that is, N When is an odd number, 2/(N-1)
It is configured to perform frequency division. FIG. 6 is an operational waveform diagram of the circuit shown in FIG. 5. Figure 6a,
b, c, and d are waveform diagrams of points with _{corresponding} symbols marked with an x mark _{in FIG} . FIG.

If the preset value is an even value, the preset input _P1 is ``0'', so the clock of the binary flip-flop 14 is inhibited and the flip-flop 14 does not operate. Therefore, the output of binary flip-flop 13
Q ₁ or ₁ is transmitted to the clock input CK ₂ of the frequency divider circuit 11 at the next stage. This clock input CK ₂
As shown in FIG. 6b, the signal has a waveform obtained by dividing the frequency of the input IN signal a into two. For example, if the preset value is "4", the signal waveform of the output OUT will be as shown in FIG. 6c. The countdown operation of the frequency dividing circuit 11 is performed by b, Q ₂ , Q ₄ , Q ₈ ,
d, and the frequency divider circuit 11 further divides the input waveform b into 1/2, that is, the waveform d is divided into 2/4 with respect to the waveform b. The waveform is counting down. Therefore the output OUT
A waveform c, which is the signal applied to the input IN divided into 1/4, is output.

On the other hand, if the preset value is an odd number, the preset input _P1 is "1", so the binary
The flip-flop 14 is supplied with a clock signal and becomes operational. As a representative example of an odd number, if the preset value is "5", the flip-flop 14 will be inverted each time a signal is sent to the output OUT. Therefore, the clock input of frequency divider circuit 11
The signal applied to CK ₂ is applied by switching the outputs Q ₁ and ₁ of the flip-flop 13 each time. This is shown in Figure 6b'. Therefore, the countdown operation of the frequency dividing circuit 11 is as follows:
As shown in b′, Q ₂ ′, Q ₄ ′, Q ₈ ′, and d′ in Figure 6, the input waveform of b′ is further divided into 1/2, that is,
The waveform of b' is counted down to the waveform of d' which is divided by 2/(5-1), and the output OUT is shown in Figure 6.
A signal with the waveform shown in c' is sent out. This is input IN
This is the fifth frequency waveform of the signal given to .

As described above, according to the present invention, only the first stage circuit that performs high-speed operation is composed of binary flip-flops suitable for high-speed operation, so it can properly operate at speeds approximately twice as high as conventional circuits. You can get a programmable counter that does.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a conventional example. FIG. 2 is an operating waveform diagram of the circuit shown in FIG. 1. Figure 3 is a circuit diagram of a presettable flip-flop. Figure 4 is a circuit diagram of a binary flip-flop. FIG. 5 is a circuit configuration diagram of a circuit according to an embodiment of the present invention. FIG. 6 is an operating waveform diagram of the circuit shown in FIG. 5. 1, 2...1/10 frequency divider circuit, 3...D type flip-flop, 11...1/5 frequency divider circuit, 12...1/10 frequency divider circuit, 13, 14...Binary flip-flop, 15...D type flip-flop, 16...
Nando circuit.

Claims (1)

[Claims] 1. In a programmable counter that divides the frequency of an input clock signal by 1/N based on a preset value N (N is a positive integer), the frequency is divided by 2/N (if N is an even number) or 2/(N
-1) A programmable counter means for performing frequency division (when N is an odd number) is provided, and a binary clock input with the above-mentioned input clock signal is provided at the front stage of this counter means.
A flip-flop 13 inputs the logical product of the logical value of the least significant digit of the set value N and the output of the counter means, and converts the output of the flip-flop so that the logical value of the least significant digit of the set value N is one of the logical values. A phase control circuit 1 which sometimes supplies the output of the binary flip-flop to the input of the counter means, and when this logical value is the other logical value, inverts the output of the binary flip-flop and supplies it to the input of the counter means.
A programmable counter comprising: 4, 16.