JPH0352041Y2 - - Google Patents

Description

[Detailed Description of the Invention] (A) Technical Field The present invention relates to a two-modulus prescaler that is used in a programmable divider or the like, and whose frequency division number is switched between two types by a control signal.

(B) Prior art In general, a programmable divider such as a PLL synthesizer is composed of a pulse swallow counter as shown in Fig. 1, which divides the clock pulse CL by N or N+1, and outputs the control signal CONT.
It has a 2-modulus prescaler 1 whose frequency division number is switched by . Then, by setting the number of times of frequency division by (N+1) in counter 2 and the number of times of the sum of the number of times of frequency division by N and the number of times of frequency division by (N+1) in counter 3, an arbitrary frequency division number can be obtained as a whole. I have to. In this pulse swallow counter, the operating speed of counters 2 and 3 may be 1/N or 1/(N+1) of the clock pulse CL, and therefore the overall operating speed is determined by the operating speed of the 2-modulus prescaler.

Therefore, a block diagram of a conventional two-modulus prescaler is shown in FIG. This circuit uses the control signal
When CONT is “0”, the division number is “4”,
When it is "1", it becomes "5".

In Figure 2, 4, 5, and 6 are clock terminals.
In the D flip-flops to which the clock pulse CL is applied to CL, the _Q1 output of the D flip-flop 4 is input to the _D2 terminal of the D flip-flop 5,
The _Q2 output of the D flip-flop 5 is input to the _D3 terminal of the D flip-flop 6. and,
_Q3 output and control signal of D flip-flop 6
The output of the AND gate 7, which inputs CONT, and the _Q2 output of the D flip-flop 5 are input to the NOR gate 8, and the output of the NOR gate 8 is input to the _D1 terminal of the D flip-flop.

FIG. 3 is a circuit diagram that realizes the block diagram of FIG. 2 using transmission gates. In the figure, I ₁₁ , I ₁₂ , . . . I ₃₂ are inverters, T ₁₁ , T ₁₂ ,
...T ₃₂ is the transmission gate,
T _o1 and T _o2 (n=1, 2, 3,) are configured as shown in FIG. 4 A and B so that they are turned on and off at mutually opposite timings.

In Figure 3, clock pulse CL is "0"
When , the signal is transmitted through paths A, B, and C shown below, and when the clock pulse CL is "1", the signal is transmitted through paths D, E, F, and G.

A (T ₁₁ → I ₁₁ → T ₁₂ ), B (T ₂₁ → I ₂₁ → T ₂₂ ), C
(T ₃₁ → I ₃₁ → T ₃₂ ), D (T ₁₂ → I ₁₂ → T ₂₁ ), E (T ₂₂ → I ₂₂ → T ₃₁ ), F
(T ₂₂ → I ₂₂ → G ₂ → T ₁₁ ), G (T ₃₂ → I ₃₂ → G ₁ → G ₂ → T ₁₁ ) Here, the inverter delay is t, the gate
If the delay of G ₁ and G ₂ is 2t, the delay is t for paths A to E, and the delay is t for path F.
In the 3t, G path, the delay is 5t, and the upper limit of the operating speed is determined by the G path. That is, in the conventional two-modulus prescaler, two logic gates 7 and 8 are included in the signal path in which a signal is to be transmitted in one clock pulse CL, and since the delay of these logic gates is large, the prescaler The drawback was that the overall operating speed was slow.

Furthermore, if the circuit configuration of FIG. 2 including the AND gate 7, NOR gate 8, and first-stage flip-flop 4 is realized using either P-type or N-type transistors, the result will be as shown in FIG. 5, but in this case, , transistors 9 and 10 must be connected in cascade,
As the number of stages increases, the delay also increases.

Therefore, when a conventional two-modulus prescaler is used in a programmable divider, the operating speed of the divider cannot be increased very much.

(c) Purpose The purpose of the present invention is to improve the operating speed of a two-modulus prescaler by reducing the delay in the signal path.

(D) Embodiment FIG. 6 is a block diagram showing an embodiment of the two-modulus prescaler according to the present invention, in which _{the two} outputs of the D flip-flop 5 and the two outputs of the D flip-flop 6 are connected.
NOR gate 11 that inputs Q ₃ output and NAND gate 1 that inputs Q ₂ output and control signal CONT
The _Q1 output of the D flip-flop 4 is input to the _D2 terminal of the D flip-flop 5, and the outputs of the NOR gate 11 and the NAND gate 12 are input to the D1 terminal of the D flip-flop 4 and the D _flip -flop 6, respectively. Input is being made to the _D3 terminal. That is, two logic gates are distributed and arranged on different signal paths to which signals are transmitted in one clock pulse CL. In addition, in this embodiment, the frequency division number is set to "4" and "5" by the control signal CONT.
Switch to .

If the embodiment shown in FIG. 6 is realized using a transmission gate as in FIG. 3, the result will be as shown in FIG. 7.

In Figure 7, clock pulse CL is "0"
When , the signal is transmitted through the paths A, B, and C shown below, and when the clock pulse CL is "1", the signal is transmitted through the paths D, E, F, and G.

A (T ₁₁ → I ₁₁ → T ₁₂ ), B (T ₂₁ → I ₂₁ → T ₂₂ ), C
(T ₃₁ → I ₃₁ → T ₃₂ ) D (T ₁₂ → I ₁₂ → T ₂₁ ), E (T ₂₂ → I ₂₂ → G ₂ → T ₃₁ )
F (T ₂₂ → I ₂₂ → G ₁ → T ₁₁ ) G (T ₃₂ → I ₃₃ → G ₁ → T ₁₁ ) In other words, in the path from A to D, the delay is t,
For the E-G path, the delay is 3t.

In reality, in addition to this, a delay between the transmission gate and the inverter and a delay between the transmission gate and the logic gate are added, so if this delay is set to 2t, the implementation example shown in Fig. 7 The delay is 5t, and compared to the delay of 5t+2t=7t in the conventional example, it is possible to improve the operating speed by about 40%.

FIG. 8 is a block diagram showing another embodiment of the present invention. In this embodiment, the NAND gate 12 of FIG. 6 is replaced with a NOR gate which receives _{the two} outputs of the D flip-flop 5 and the control signal CONT. 13
and also the Q ₃ output of D flip-flop 6.
It is input to NOR gate 11.

If the embodiment of FIG. 8 is realized using either a P-type or an N-type transistor, the circuit configuration including the NOR gate 11 and the first stage D flip-flop 4 will be
As shown in the figure, the number of transistor stages is reduced compared to the conventional example shown in FIG. 5, and therefore the delay is reduced. The circuit configuration including the NOR gate 13 and the final stage D flip-flop 6 is also the same as that shown in FIG.

Next, an application example of the embodiment shown in FIGS. 6 and 8 is shown in FIGS. 10 and 11.

FIG. 10 is an example of a 2-modulus prescaler using the embodiment of FIG. 6 and switching the division number between "8" and " ₉ ". A T flip-flop 14 whose output is input to the T terminal and a NOR gate 15 which inputs the Q output of the T flip-flop 14 and a control signal CONT8 for switching the frequency division number to "8" or "9" are added. 15 output as control signal CONT
The signal is input to the NAND gate 12 as a signal. In this embodiment, when the control signal is "0", the frequency is divided by 9, and when the control signal is "1", the frequency is divided by 8.

Also, Fig. 11 is an example of a 2-modulus prescaler that uses the embodiment shown in Fig. 8 and switches the dividing number between "16" and "17", and operates at the falling edge of the _Q2 output. T flip-flop 16 and T
T flip-flop 17 that operates at the rising edge of the Q _A output of flip-flop 16 and a control signal for switching the frequency division number to "16" or "17"
A NOR gate 18 that inputs the CONT 16 and the Q _B output of the T flip-flop 17, and a NAND gate 19 that inputs _{the A} output of the T flip-flop 16 and the output of the NOR gate 18 are added to the embodiment shown in FIG. , the output P of the NAND gate 19
is input as the control signal CONT.

Therefore, a timing chart of the embodiment shown in FIG. 11 is shown in FIG. 12.

In FIG. 11, when the control signal CONT16 is "1", the output of the NOR gate 18 is "0",
Therefore, the output P of the NAND gate 19 becomes "1", so the output of the NOR gate 13, that is, the _D3 input, is
It becomes "0" regardless of the state of _Q2 output, and _Q3 output remains "0". Therefore, the output of NOR gate 11 is determined only by the Q ₂ output, and Q ₂
When the output becomes "0", the _Q1 output rises at the rising edge of the next clock pulse CL. That is, in this case, the _Q3 output is not generated, and the same operation as in the case of only two stages of flip-flops 4 and 5 is performed, so that the clock pulse CL is divided into four.
Moreover, even if the control signal CONT16 is "0",
Since the output P of the NAND gate 19 is "1" except when both the Q _A output and the Q _B output are "0", the clock pulse CL is similarly divided by four.

However, the control signal CONT16 is "0" and Q _A
When the output and Q _B output are both “0”
The output P of NAND19 becomes "0". in this case,
When the _Q2 output rises and the _Q2 output becomes "0",
Since the output of the NOR gate 13, ie, the _D3 input, becomes "1", the _Q3 output rises at the next rising edge of the clock pulse CL after the _Q2 output rises.
Therefore, the _Q3 output becomes "1", and the output of the NOR gate 11, that is, the _D1 input, becomes "0" regardless of the state of the _Q2 output, and the next clock pulse after the _Q3 output becomes "0". The _Q1 output will rise when CL rises. That is, in this case, 2
Since the _two outputs of the flip-flop 5 in the third stage are transmitted to the flip-flop 6 in the third stage, this flip-flop 6 causes the rise of the _Q1 output to be 1.
Delayed by clock pulse CL. Therefore, when the output P of the NOR gate 19 becomes "0", the _Q3 output is generated and the clock pulse CL is divided by five. In this way, the frequency division by 4 and the frequency division by 5 are switched by the output P of the NOR gate 19.

By the way, the output P of the NOR gate 19 is "0"
This occurs only when the control signal CONT16 is "0" and both the Q _A output and the Q _B output are "0". Q _A output and Q _B output are (1,0),
After taking the three states (0, 1) and (1, 0), it becomes the state (0, 0), and in this state,
The frequency division by 5 and the frequency division by 4 are switched depending on whether the control signal CONT16 is "0" or "1". Therefore, as shown in FIG.
When CONT16 is "0" and only one cycle after becoming "1", the clock pulse CL is divided by 17, and when CONT16 is "1" and only one cycle after becoming "0", the clock pulse CL is divided by 17. Divide clock pulse CL by 16. In this way, the frequency division by 16 and the frequency division by 17 are switched by the control signal CONT16.

(E) Effects Since the two-modulus prescaler according to the present invention has logic gates distributed and arranged on different signal paths, the delay can be reduced, and the operating speed can therefore be improved. Therefore, if the two-modulus prescaler according to the present invention is used in a programmable divider, it becomes possible to operate the divider at high speed.

[Brief explanation of drawings]

Fig. 1 is a schematic block diagram showing a pulse swallow counter, Fig. 2 is a block diagram showing a conventional 2-modulus prescaler, and Fig. 3 is a block diagram showing a conventional 2-modulus prescaler. The realized circuit diagram, Fig. 4 A and B, is a circuit diagram showing the configuration of the transmission gate, and Fig. 5
The figure is a circuit diagram of the main part of a circuit that realizes the 2-modulus prescaler shown in Figure 2 using either P-type or N-type transistors, and Figure 6 shows an embodiment of the 2-modulus prescaler according to the present invention. 7 is a circuit diagram that realizes the embodiment of FIG. 6 using a transmission gate, FIG. 8 is a block diagram showing another embodiment of the present invention, and FIG. 9 is a circuit diagram of the embodiment of FIG. 8. A main part circuit diagram of a circuit in which the embodiment is realized using either P-type or N-type transistors, FIG. 10 is a block diagram showing an application example of the embodiment of FIG. 6, and FIG. 11 is a diagram of the circuit shown in FIG. FIG. 12 is a block diagram showing an application example, and FIG. 12 is a timing chart of the application example of FIG. Explanation of main drawing numbers, 1...2 Modulus prescaler, 4,5,6...D flip-flop, 7...
...AND gate, 8, 11, 13, 15, 18...
...NOR gate, 12,19...NAND gate,
14, 16, 17...T flip-flop.

Claims (1)

[Scope of utility model registration request] a second flip-flop to which the output signal of the first flip-flop is input; a first logic gate to which the output signal of the second flip-flop and a control signal for switching the frequency division number are input; and a second flip-flop to which the output signal of the first logic gate is input. 3 flip-flops and the third
The first,
The first logic gate and the second logic gate are arranged in different transmission paths among a plurality of transmission paths for transmitting signals using clock pulses applied to the second and third flip-flops. 2 modulus prescaler.