JPS61164323A - Timing pulse forming circuit - Google Patents

Abstract

PURPOSE:To form two kinds of timing pulses by connecting the 1st gate input terminal respectively to a terminal to which an input pulse is applied via a signal delay means and providing an OR gate and AND gate to which the 2nd gate input terminal is connected directly. CONSTITUTION: When an input pulse P1 is applied, a logical level at an output terminal 4 changes from H to L level in an NOR gate 6. On the other hand, the logical level of an output terminal 5 of an NAND gate 7 goes to H level, and when a delay time tau4 set by inverters 10, 11 is elapsed, the level changes from H to L level. When the input pulse P1 changes from H to L level, the logical level of the output terminal 5 changes immediately from L to H level. On the other hand, the logical level at the output terminal 4 changes to H level when the delay time tau3 set by the inverters 8, 9 is elapsed in the NOR gate 6.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a timing pulse forming circuit capable of forming two types of timing pulses having different timings from one type of pulse signal.

In conventional digital logic circuits, cases often occur in which two different timing pulses are formed from one type of pulse signal and the circuit operation is controlled by these timing pulses.

FIG. 3 is a block diagram showing a conventional timing pulse forming circuit used to form such timing pulses, and shows a terminal 1 to which a pulse signal is applied.
Delay circuits 2 and 3 having different delay times are connected to each other, and timing pulses are taken out from output terminals 4 and 6 connected to the output ends of these circuits.

FIG. 4 is a timing diagram showing the relationship between the input pulse P1 and the timing pulses P2 and P3 obtained at the output terminals 4 and 6 in the timing pulse forming circuit,
Assuming that the delay times of delay circuits 2 and 3 are τ1 and τ2, the timing pulse P1 is a pulse whose rise and fall times are delayed by a time τ1 from the input pulse's rise time t1 and fall time t2, respectively. Similarly, the timing pulse P is a pulse delayed by the time τ2 with respect to the times t1 and t2.

Problems to be Solved by the Invention The timing pulses P2 and P3 formed by the conventional timing pulse forming circuit have a phase shifted relationship as shown in FIG.

Therefore, there is a relationship between the circuit operation controlled by the pulse width of timing pulse P2 and the circuit operation controlled by the pulse width of timing pulse P3, in which the latter circuit operation is completed during the former circuit operation. It cannot be established. Therefore, conventional timing pulse forming circuits cannot be used in digital logic circuits that require circuit operation control in this manner.

Means for Solving the Problems The timing pulse forming circuit of the present invention has a first gate input terminal connected to a terminal to which an input pulse is applied via a signal delay means, and a second gate input terminal connected directly to a terminal to which an input pulse is applied. and an AND gate to which a first gate input terminal is connected via a signal delay means and a second gate input terminal is directly connected to a terminal to which the input pulse is applied. , the first and second timing pulses are generated at the output terminals of the OR gate and the AND gate.

According to the timing pulse forming circuit of the present invention configured in this way, the second timing pulse to the output terminal of the AND gate is generated earlier than the first timing pulse to the output terminal of the OR gate. The onset of the outbreak is delayed,
Further, two types of timing pulses can be formed by establishing a relationship in which the generation of the second timing pulse ends earlier than the time when the generation of the first timing pulse ends.

EMBODIMENTS Below, the structure and operation of the timing pulse forming circuit of the present invention will be explained in detail with reference to FIGS. 1 and 2.

FIG. 1 is a circuit diagram showing an example of the timing pulse forming circuit of the present invention, in which one of the gate input terminals is directly connected to the terminal 1 to which a pulse signal is applied, a NOR gate 6 and a NAND gate 7. Inverters 8 and 9 are connected in series between the other gate input terminal of NOR gate 6 and terminal 1, and an inverter is connected between the other gate input terminal of NAND gate 7 and terminal 1. 10
and 11 are connected in series, and further, timing pulse output terminals 4 and 5 are connected to the output terminals of the NOR gate 6 and NAND gate 7.

The operation of the timing pulse forming circuit configured as described above and the relationship between the input pulse and the timing pulse are shown in FIG. 2, together with a timing diagram of the input pulse P1, the timing pulse P4 obtained at the output terminals 4 and 6, and the Rahini P6. Please refer to the following for a detailed explanation.

The input pulse P1 shown in FIG. 2 is applied to the terminal 1, and at time t, the voltage level changes from the high level (hereinafter referred to as "L I+ level") to the low level (hereinafter referred to as "H" level).
When the input pulse directly connected to the gate input terminal is given priority in the NOR gate 6, the logic level of the output terminal 4 immediately changes from the "H" level to the IT L I+ level.On the other hand, the NAND gate 7 The time t1K of the two gate input terminals of the logic fM level is ``
Therefore, the logic level of the output terminal 5 is H'' level. By the way, when the delay time τ4 set by inverters 10 and 11 has elapsed, the output level of inverter 11 becomes ff.
The logic level of both gate input terminals changes to HI+ level, and the logic level of output terminal 5 changes from "L" level to "H" level.

Next, at time t2, when the input pulse P1 changes from II HII level to L'' level, only the logic level of the gate input terminal to which the input pulse is directly connected changes to L level in HAND gate 7, so that the output The logic level of the terminal 5 immediately changes from the LI+ level to the "H" level. On the other hand, in the NOR gate 6, the logic level of the gate input terminal to which the input pulse is directly connected similarly changes to "L" at time t2. However, the output level of the inverter 9 is maintained at the H level, and this level is given priority.

Therefore, the logic level of the output terminal 4 is held at the n L 11 level. Then, from time t2, the inverter 8
When the delay time τ3 set by and 9 has elapsed, the output level of the inverter 9 becomes the "LI+" level, and at this point, the logic level of the output terminal 4 changes to the "H" level.

By repeating the above operations, timing pulses P4 and P6 shown in FIG. 2 are formed.

In the above explanation, a two-stage cascade connection of inverters is shown as a signal delaying means, but it is possible to change the number of stages or to use other signal delaying means such as a continuous charge type delay circuit instead of an inverter. It is possible to make changes such as: However, the OR gates and AND gates can also be OR gates and AND gates.

Effects of the Invention According to the present invention, a pulse is formed based on an input pulse, and
A first timing pulse having a predetermined pulse width, and a second timing pulse that is generated within the generation period of the first timing pulse and whose falling and rising timings do not match those of the first timing pulse. A timing pulse is formed.

Therefore, a circuit that executes a circuit operation controlled by the pulse width of the second timing pulse P6 during a circuit operation controlled by the pulse width of the first timing pulse P4, and completes this circuit operation. Motion control is achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the configuration of the timing pulse forming circuit of the present invention, FIG. 2 is a timing diagram showing the relationship between input pulses and timing pulses in the same circuit, and FIG. 3 is a diagram showing the configuration of a conventional timing pulse forming circuit. Block diagram shown, No. 4
The figure is a timing diagram showing the relationship between input pulses and timing pulses in the same circuit. 1... Input pulse application terminal, 2.3... Delay circuit,
4, 5 - Timing pulse output terminal, 6...
NOR gate, 7...NAND gate, 8-11
...Inverter. Name of agent: Patent attorney Toshio Nakao and 1 other person6-
--NOR gate 7---NANO gate 8~ll-m-invert Figure 2

Claims (1)

[Claims] first and second delaying the input pulse by a predetermined time;
a signal delaying means, an OR gate having a first gate input terminal to which the output of the first signal delaying means is input, and a second gate input terminal to which the input pulse is directly input; and a first gate input terminal. an AND gate to which the output of the second delay means is input, and a second gate input terminal to which the input pulse is directly input; A timing pulse forming circuit characterized in that it generates first and second timing pulses.