JPH01108809A - Delay line - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution without fluctuating the pulse width on one and same path and division of a signal into two paths by offering a delay signal of the input signal to an output of a flip-flop. CONSTITUTION:The title line is provided with on exclusive OR circuit 4 receiving an input signal and a signal being the result of retarding the input signal by a 1st delay circuit A and generating an output at a level change point of the input signal, a 2nd delay circuit B connected to the output, and a flip-flop FF set by the AND between the output of the 2nd delay circuit B and the input signal and reset by the AND between the output of the 2nd delay circuit B and the inversion of the input signal. Then the delay signal of the input signal is given to the output of the flip-flop FF. Thus, the input pulse width is reproduced accurately and the rate of the delay part occupied to the entire chip area is nearly halved in comparison with the case of two divided paths.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a delay line, which is widely used in electronic devices such as /'Psonal computers and printers, and is intended for timing control of control signals, clocks, etc. used as.

(Prior art) A delay line was developed for the purpose of delaying digital signals by a necessary amount of time, and is currently used as a general-purpose IC.

A hybrid type delay line made by combining C is widely and generally used. However, there are restrictions on the size of hybrid daytime lines, and they cannot be made smaller than monolithic ones. Therefore, it is possible to make the delay line smaller and lower in cost by configuring the delay line monolithically. However, when configuring a monolithic delay line, the delay and delay portions are made by integrating circuits using R and C or transistors and C, or by connecting logic darts in multiple stages, so the area is much larger than that of a normal logic circuit. Requires.

Conventional methods either pass the input signal as it is through delay circuits such as R and C, or they use an inverter to generate two types of signals: inverted and non-inverted, both of which have a rising edge or a falling edge. Only one edge was delayed and the waveforms were finally synthesized using a flip-flop. In the former, the pulse width of the input signal fluctuates due to the difference in delay time between rising and falling, while in the latter, by dividing into two types and delaying them separately, twice the delay circuit is required, which increases the area.

An example of the former is shown in FIG. 6, and an example of the latter is shown in FIG. Moreover, Japanese Patent Application Laid-Open No. 61-150406 is an example of the latter.

(Problems to be Solved by the Invention) In the prior art method in which the input signal is directly passed through an integral delay circuit composed of R, C, etc., due to the difference in delay time between rising edge and falling edge. If the pulse width of the input signal cannot be faithfully transmitted to the output, a very short time delay may be effective through design optimization. In addition, the input signal is passed through two types of signals, inverting and non-inverting, using separate paths, and the rise or fall of both signals is delayed. This method prevents fluctuations in the p i44 pulse by using only one of the rising edge and the falling edge of the i4 pulse, but by dividing the pulse into two paths, the delay part is If we try to create a delay line that delays the delay by several hundred nanoseconds, which is twice as necessary, it would require a very large area, and because of the separate paths, it would be affected by variations in the elements.

It is an object of the present invention to provide a delay line capable of delaying the input signal by several hundred nanoseconds without doubling the area of the delay portion and without changing the pulse width of the input signal.

(Means for Solving the Problems) The feature of the present invention is that the input signal and the first delay circuit' (A
) is input, and generates an output at the point of change in the level of the input signal, and a second delay circuit (BJ and second delay circuit) connected to the output of the exclusive OR circuit (111) and an input signal, and reset by a logical AND of the output of the second delay circuit (B) and an inversion of the input signal, and the flip-flop is on a delay line that provides a delayed signal of the input signal to the output of the .

(Structure and operation of the invention) The present invention provides a method for realizing a delay circuit for delaying a digital signal by a necessary time using a monolithic IC, and the circuit structure thereof will be described below. .

When a digital input signal is passed through the base pulse generation circuit shown in Figure 1, which takes an exclusive OR of the signal that has passed through a delay circuit to delay it by a certain amount of time and the signal as it is, the waveform at each point is As shown in Figure 2, when the input rises, K/
When the signal with 4 pulse width T and the falling edge are ?J? Loose width T2
Two noculus of signals are formed at the output stage 4 of FIG. Here, the delay circuit used in Fig. 1 has a relatively short delay time, and at the same time, the rising signal of the signal can be generated at the rising edge of the signal (as shown in T2). The signal is divided into two signals, the pulses generated at the time of the signal, and are input to the delay circuit following the output stage (4) in Figure 1.This delay circuit only needs to be concerned with the rising edge. , even if the Nockles width varies, these two signals allow the set/reset flip meph log to reproduce the same pulse width as the input signal.

However, the question is iJ? When pulses are continuous, which signal is to be used as a set input signal and which signal is to be used as a reset input signal. If the input signal is low/loose, it is necessary that the reset signal enters first and the set signal enters later in the 7rip/70seg of the output stage. One of the features of the present invention is that the set/reset input signal is ANDed with the non-delayed input signal so that it can be divided into set input and reset input. This is possible if the total delay time is shorter than the pulse width of the input signal. For example, input high-no-J?
Is there a J in Luz that was formed when she stood up? Since only the signal is included, it can be used as a set input signal by ANDing the high input signal.

The reset input signal can also be created by inverting the low before the next input/4' pulse enters the input terminal and performing an AND. This condition that the overall delay time is shorter than the pulse width of the input signal is the same for the conventional two-path dividing method.

Therefore, according to the present invention, the delay circuit can be constructed with half of the conventional delay circuit without dividing the signal into two paths and without varying the pulse width on the same path.

(Example) FIG. 3 shows an example of the present invention. Here, when the waveform shown in Figure 4 1 is input to the digital signal input terminal (1), the exclusive OR output of (4) is shown in the pulse generation circuit in Figure 1 and the waveforms of each part in Figure 2. Two signals are formed on the same path: a signal with a pulse width T, which is generated when the input signal 1 rises, and a signal with a pulse width T2, which is generated when the input signal 1 falls.

These pulse widths T and T2 are determined by the following: When the delay circuit A is formed by a basic inverter and an integrating circuit as shown in FIG.
It is determined by the load capacitance, while the fall is determined by the channel resistance of NMO8, the load resistance, and the load capacitance. Therefore, when designing, make sure that the channel resistance of PMO8 and NMO8 are equal.
Even if MO8 and NMO8O sizes are determined, they are not necessarily equal due to variations in process and the like. For that purpose, T
, and T2, which are considered to have different widths. The first method described in the conventional method simply connects these in multiple stages, so for the reasons mentioned above, the input signal ()
9. The pulse width fluctuates in the output. This method is the first
In the pulse generation circuit shown in the figure, the input signal is divided into two signals: a signal with a pulse width T that rises when the input rises, and a signal with a pulse width T2 that rises when the input falls. All you need to do is focus on the delay time. In addition, by passing the same delay circuit B through the same path, there is no need to create two paths with the same delay time of the delay circuits C and D shown in the conventional system as shown in FIG. 5, and the area can be reduced. , D due to variations in elements does not need to be corrected.

In addition, as a method of distributing the two signals generated by (4F) to the set input and reset circuit of the set/reset 7-reset fX flop in the subsequent stage, by ANDing the input signals using AND gate 1.2, (s), (9) in Figure 4
) By creating set and reset signals as shown in uO), an output signal with the same pulse width as the input can be obtained by delaying the required time for uO).

Furthermore, by adding a reset circuit in addition to AND gates 1 and 2, initial values can be set.

Although 0MO8 has been taken as an example of the embodiment of the present invention, it is not limited to (1) and may be configured with bipolar.

(Effects of the Invention) According to the present invention, in a monolithic delay line that delays a digital signal for several hundred nanoseconds or more, the input/f pulse width can be accurately reproduced, and the ratio of the delay portion to the entire chip area can be reduced. This can be approximately halved compared to the case of dividing into two routes.

[Brief explanation of the drawing]

Fig. 1 is a conventional pulse generation circuit, Fig. 2 is an operating waveform diagram of Fig. 1, Fig. 3 is a delay line circuit according to the present invention, Fig. 4 is an operating waveform diagram of each part of Fig. 3, and Fig. 5 6 shows a conventional delay line circuit and its operating waveform diagram, and FIG. 6 shows a delay circuit using a CMO8 basic inverter circuit. In Fig. 3, 1: input terminal, 4: exclusive OR circuit, 8, 9: AND circuit, A, B: delay circuit, FF: flip-flop, 1
0: Output terminal.

Claims (1)

[Claims] An exclusive OR circuit that receives an input signal and a signal delayed by a first delay circuit (A) and generates an output at a point where the level of the input signal changes; It is set by the AND of the connected second delay circuit (B), the output of the second delay circuit (B), and the input signal, and the output of the second delay circuit (B) and the inversion of the input signal are set. and a flip-flop that is reset by a logical product of , and provides a delayed signal of an input signal to the output of the flip-flop.