JPS6259415A - Multi-input logic circuit - Google Patents

Abstract

PURPOSE:To prevent generation of noise waveform except an expected waveform by using a multi-input logic element including an inverter for an operation means so as to form a logic circuit. CONSTITUTION:Input logic signals A, B, D are inputted directly and input logic signals C, E are inputted via inverters 12, 13 to a gate of a multi-input NAND 14, which applies logic operation and the output is an operation result Y. Through the constitution above, since the logic operation is applied by using the multi-input logic element, no delay time is caused to each input signal and the operation is applied different from the use of plural less-input logic elements. Thus, the generation of noise waveforms other than the expected value such as spike waveform is prevented as the output waveform, the malfunction of the multi-input logic circuit is prevented and high speed stable logic operation is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to multi-input logic circuits for integrated circuits.

(Prior Art) An example of a conventional multi-input logic circuit will be described with reference to FIGS. 2 and 3.

FIG. 2 shows a circuit diagram of an example of the configuration of a conventional multi-input logic circuit, in which five input logic signals A to E are passed through four logic elements 1 to 4 to perform a single logic operation. , the logical formula for the operation result Y is as follows:
(1).

FIG. 3 shows a simplified timing chart for explaining the operation of the conventional multi-input logic circuit. The input logic signals A-, E, the calculation result Y, and the signal waveforms at intermediate points 5 to 7 shown in FIG.
8 to 10 in the figure indicate the delay time of the output signal with respect to the input signal of the logic elements 1, 2.3, respectively. The waveform Y' shown in FIG.
The output waveform expected from the logical operation result is,
In reality, the input signal 7 to the final stage logic element (2-man 0R) 4 is changed from the expected ideal input signal 7' to the logic element 1.
Since the output waveform is delayed by a total delay time 11, which is the sum of the delay times 8 to 10 of .about.3, the output waveform is different from the waveform Y and the expected output waveform Y'.

(Problems to be solved by the invention) In recent years, methods of designing integrated circuits by combining standardized logical units such as r-dore arrays and standard seven modules have become popular. When performing a logical operation on a force, as in the conventional example, variations in the internal delay of each signal occur due to the difference in the depth of each logic/9th path.As a result, the output waveform may have a wave other than the expected value or a wave other than the expected value. There was a problem in that unnecessary waveforms such as waveforms were generated, causing circuit malfunctions.
This is a problem that often occurs in e-17 rays, etc., which are designed by combining logical units with a fixed delay time.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a multi-input logic circuit that does not consist of a plurality of input logic elements as in the past, but uses an arithmetic means. Another object of the present invention is to provide a multi-input logic circuit with shallow logic depth configured using multi-input logic elements including inverters.

(Function) According to the present invention, since the logical operation Since the calculation can be performed without causing a spike waveform in the output waveform, it is possible to prevent the spike waveform from occurring in the output waveform.

(Embodiment) An embodiment of the multi-input logic circuit of the present invention will be described with reference to the circuit diagram shown in FIG. In FIG. 1, the input logic signals A, B, and D are directly connected to the input logic signal C and the multi-input NAND 14 (71'-
A logical operation is performed using the multi-input NAND 14, and the operation result Y is output.

The multi-input logic circuit of the present invention shown in FIG. 1 and the conventional multi-input logic circuit shown in FIG. 2 are logically equivalent, as proven by the following logical formula.

Y = (A-B 10)・D + E
(1) =AfB〇-D+E =A-B-C-D-1-E =A+B+C+D-Hi: =to-B-C-D-g (z) That is, equation (1) is shown in Figure 2. Equation (2) represents the logical formula of the conventional multi-input logic circuit shown in FIG. Although it is logically equivalent to a logic circuit, the logic depth is clearly different. In other words, the maximum logic depth difference of the conventional multi-input logic circuit is 3 levels (signals A, B vs. signal E).
), whereas the maximum logic depth difference of the multi-input logic circuit of the present invention is Lebel, which is generally only the Lebel of an inverter with less delay. For the above reasons, it is clear that the multi-input logic circuit of the present invention is effective in preventing the generation of spike waveforms caused by internal delay variations. That is, the multi-input logic circuit of the present invention has a third
This is an effective means for obtaining the expected output waveform Y' shown in the figure. Furthermore, the multi-input logic element 14 shown in one embodiment of the multi-input logic circuit of the present invention is one that is normally registered as a standard library such as a dirt array, and can be easily implemented. Moreover, according to the multi-input logic circuit of the present invention, the speed required for general operations is improved over conventional multi-input logic circuits.

(Effects of the Invention) According to the present invention, by performing a logic design that uses multi-input logic elements, it is possible to prevent the generation of noise waveforms other than the expected value, such as the 9-strip waveform, and to integrate the integrated circuit. This has the effect of preventing malfunctions in multi-input logic circuits and performing logic operations at high speed and stability.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a multi-input logic circuit for an integrated circuit according to the present invention, FIG. 2 is a circuit diagram of a conventional multi-input logic circuit, and FIG. 3 explains the operation of a conventional multi-input logic circuit. The timing chart for this is shown below. 1.2.3.4...Logic element, 5,6.7...Intermediate point, 8...Delay time of output signal with respect to input signal of logic element 1, 9...Input of logic element 2 Delay time of output signal with respect to signal, 10...Delay time of output signal with respect to input signal of logic element 3, 11...Total delay time, 12
j13...Inverter, 14...Multiple input rabbit, A,
B, C, D, E...input logic signal, Y...output waveform (calculation result), Y'...expected output waveform. Fig. 1j 12.13...Invar 7 14 °゛Multiple input, l'7NAND Fig. 2

Claims (1)

[Claims] 1. A multi-input logic circuit characterized in that the logic circuit is configured using a multi-input logic element including an inverter as an arithmetic means.