KR960005684Y1 - One-shot pulse generator - Google Patents

Abstract

None.

Description

One short pulse generating circuit

1 is a circuit diagram showing an example of a conventional one short pulse generation circuit.

2 is an output waveform diagram of FIG.

3 is a symbol state diagram of the present invention in which a dummy pin is formed in an end gate.

4 is a true state diagram of the input and output of FIG.

5 is a physical layout diagram of an input and gate according to the present invention.

6 is a circuit design embodiment using the one-shot pulse generation dedicated cell of the present invention.

7 is a layout diagram of the logic circuit diagram shown in FIG.

8 is an output waveform diagram of each logic gate according to the present invention.

The present invention relates to a one shot pulse generator circuit which is frequently used in logic circuit design, and when a signal is generated, it is synchronized by the signal to generate a certain width of active low or active high ( active high) circuit for outputting a pulse signal.

In logic circuit design using a cell library, the one-short pulse generation circuit can be simply designed using a gate array cell or a standard cell library, which is a two input NAND. One pulse signal is generated at an output terminal by using a time delay difference between two input signals input to a NAND gate or an AND gate.

FIG. 1 is a circuit diagram showing an example of a conventional one short pulse generation circuit, and FIG. 2 is a waveform diagram showing the input signal and the output signal of FIG. The pulse width of the output OUT waveform corresponds to the time delayed by the three inverting gates G1 to G3 in FIG. 1.

However, when the one short pulse generation circuit shown in FIG. 1 is used, the following technical problem occurs.

First, various factors, such as resistance or parasitic capacitance of a metal wire constituting a circuit as a process variable, and errors in length and width of a transistor, cause a change in delay time. ,

Second, when the automatic layout wiring is performed with the automatic layout tool in FIG. 1, the length of the metal wire from the input terminal N1 to the terminal B of the two input and gates is equal to the inversion gate G1 at the terminal N1. It can be considerably longer than the length of the metal wire to the input terminal. In this case, the stable pulse width desired by the designer cannot be obtained because the delay time of the signal reaching the two input and gate terminals B half or cancels the inversion gate delay effect.

As the above two formations become more severe with the micron or less process technology, the circuit configuration of FIG. 1 is avoided as much as possible in the general logic design concept, or must be verified by performing a transistor level simulation. In this case, too, it is inconvenient to verify each circuit.

Accordingly, an object of the present invention is to provide a one-shot pulse generation circuit suitable for a circuit design that can efficiently design logic with fewer logic gates and requires faster operation by solving the above problems.

In the one short pulse generation circuit of the present invention for achieving the above object is a one short pulse generation circuit for outputting an active low or active high pulse signal of a predetermined width by inputting a synchronized signal,

A logic operation means having first and second input terminals and one output terminal, a dummy terminal connected to the first input terminal of the logic operation means,

And natural means connected between the first input terminal and the first input terminal to which the dummy terminal is connected.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating an additional dummy pin DUM formed in a general AND gate symbol, and an arrow indicates that the dummy pin DUM is connected to a terminal B therein.

4 shows the truth table of the logic circuit of FIG.

5 is a diagram illustrating a physical layer of a lay cell, and a dummy pin DUM is installed next to the terminal B, and the terminal B and the dummy pin DUM are connected by a metal wire. In this way, the auto layout tool prepares to recognize all four pin targets, including the dummy pin (DUM).

FIG. 6 prepares the one-short pulse application circuit to recognize all four pin targets using the logic symbols of FIG.

FIG. 6 illustrates a one-shot pulse application circuit using the logic symbols of FIG. 3. FIG. 7 illustrates the physical layout of FIG.

Referring to the automatic layout arrangement wiring structure of FIG. 7, the signal input to the terminal IN must pass through the terminal B in order to reach the inlet of the inverting gate G1, which means that the AND gate input terminal B is the inverting gate ( Since the logic high voltage is reached at the same time point or faster than the input terminal A of G1), the inversion gate delay cancellation due to excessive metal line delay is eliminated.

The physical layout cell of FIG. 5 can only be used by setting pin targets in a conventional physical layout without using extra silicon, and logic symbols can also be described in accordance with the true state diagram.

In the above embodiment, only the AND gate has been described as an example, and the OR, the NOR, the NAND, the exclusive OR, the XOR, and the XNOR gate are the same in the same way. When the physical layout is configured, various pulses are obtained as shown in FIG.

To achieve a safe pulse width, a counter circuit is usually used, which is synchronized by a clock signal. This method requires the use of a large number of gates, which requires a lot of time in design, complexity, chip size, and test.

By using the circuit of the present invention, it is possible to design an efficient logic with few logic gates in the circuit design, and it reacts immediately when a signal is applied, which is suitable for designing a circuit requiring faster operation.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions, and additions through the spirit and scope of the present invention disclosed in the appended claims.

Claims (2)

(correction) In a one-shot pulse generation circuit for outputting an active low or active high pulse signal of a predetermined width with a synchronized signal as an input, Logic operation means having first and second input terminals and one output terminal, a dummy terminal connected to the first input terminal of the logic operation means, And a delay means connected between the first input terminal and the second input terminal to which the dummy terminal is connected. (correction) The method of claim 1, And said delay means comprises an odd number of inverters.