JPH02125519A - Cmos buffer circuit - Google Patents

Abstract

PURPOSE:To output a signal without delay at charging of a load capacitance by providing a circuit causing a delay in a signal so that lots of buffer circuits are operated simultaneously and the discharge current of the load capacitance is not supplied to an earth line simultaneously. CONSTITUTION:An output signal of a NAND gate 8 is retarded by inverters 4, 5 and a buffer circuit 1 and two inputs are at high level at the input of the NAND gate 8. In this case, an output of the NAND gate 8 goes to a low level to cut off an N-channel transistor(TR) 9 for a delay time t41. On the other hand, the 2nd input signal from an input terminal 12 after being supplied is operated with a delay of time td2-td1. On the other hand, in the case of charging the load capacitance, since a period being at a high level of both the input signals at the input of the NAND gate 8 does not take place, the delay circuit is not operated and a waveform of a 2nd output signal is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS buffer circuit, and more particularly to a buffer circuit used in a circuit portion in which many outputs change simultaneously.

[Conventional technology]

Conventionally, many CMOS buffer circuits of this type have been used in semiconductor integrated circuits. In a circuit using a large number of CMOS buffer circuits, if a plurality of inputs change in phase at the same time, the discharge current of each load capacitance flows into the ground line of all the buffer circuits at the same time. In particular, in the output buffer circuit section and decoder buffer circuit section that use a large number of buffer circuits, the discharge current becomes extremely large, so the potential of the ground line is instantly raised, causing other circuits such as sense amplifiers that share the ground line. This may cause malfunction. To deal with this, two measures have been taken as follows.

(1) Provide the ground wiring for the buffer circuit separately from the ground wiring for other circuits.

(2) Add a time constant circuit to reduce the operating speed of the buffer circuit so that a large current does not instantly flow into the ground wire.

[Problem that the invention seeks to solve]

The countermeasures against the discharge current of the load capacitance of the conventional buffer circuit described above have the following problems.

(1) Particularly in large-capacity storage circuits, if the chip area becomes large, the yield and collection accuracy will decrease, so separate wiring cannot be provided.

(2) When adding a time constant circuit, the operating speed of the circuit must be reduced, so it cannot be used for applications that require high speed.

The purpose of the present invention is to solve such problems and to provide a CMOS buffer circuit that does not slow down the speed when charging the load capacitance in all layers even if all the inputs change simultaneously when a large number of CMOS buffer circuits are used. It is about providing.

[Means for solving problems]

The configuration of the present invention is such that, in a CMOS buffer circuit having at least a pair of first and second buffer circuits, a holding signal is generated by the logical sum or logical product of the input signal of the first buffer circuit and its output signal. The second buffer circuit is characterized in that it includes a logic gate that generates a signal, and an inhibit circuit that temporarily inhibits the input signal of the second buffer circuit based on a holding signal of the logic gate.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a waveform diagram explaining the operation of FIG. 1. The buffer circuit of this embodiment consists of an input control circuit section 3, which is shown as a pair of dotted lines, and includes a CMOS inverter 1.2, delay inverters 4, 5, 6.7, and a NAND gate 8. It is composed of an N-channel transistor 9.

A case will be described in which the first input signals from each input terminal 11, 12 change simultaneously. In this case, the input waveforms are the same. The input signal from the input terminal 11 is supplied to the CMOS inverter 1 through the inverter 4.5 in the second stage, and is simultaneously input to the NAND gate 8. This NAN
The output signal of the D gate 8 is transmitted to each inverter 4.5. It is delayed by the buffer circuit 1, and both outputs are at a high level at the input portion of the NAND gate 8. At this time NA
The output of the ND gate 8 becomes low level, and the N-channel transistor 9 is cut off for a delay time t-1 (
Figure 2 (A) NAND output).

On the other hand, the second input signal from the input terminal 12 has the same waveform as the first input signal, but when that input signal rises, the signal at the second output terminal 14 is output by the N-channel transistor 9. Since it is cut off, high level signals are held.

That is, when the N-channel transistor 9 is turned on again with the second output signal at a high level for the cutoff period, the delay time td2 after the input signal is supplied.
It starts operating with a delay of jdl. Buffer circuit 1 like this
Since a time difference of delay time td2tdl occurs between the buffer circuit 2 and the buffer circuit 2, they do not operate simultaneously.

On the other hand, when charging the load capacitance, that is, when the first and second output signals rise, there is no period in which the re-input signal is at a high level at the input part of the NAND gate 8, so the NAND gate The output waveform of transistor 8 remains at a high level, and N-channel transistor 9 remains on (FIG. 2(B)). Therefore, in this case, the delay circuit does not operate, and the waveform of the second output signal is obtained.

FIG. 3 is a circuit diagram of a second embodiment of the present invention, and FIG. 4 is a circuit diagram of a second embodiment of the present invention.
FIG. 3 is a waveform diagram illustrating the operation shown in FIG. In this embodiment, in order to prevent the output signals of at least two inverter circuits from changing simultaneously from low level to high level, one of the two buffer circuits used as a pair is provided with a delay.

In this example, in order to prevent instantaneous fluctuations in the power supply line due to large current flowing from the power supply line due to multiple buffer circuits charging the load capacitance at the same time, a delay circuit and a circuit that temporarily holds the input signal are used. NOR gate 20
Since the delay circuit does not operate when the load capacitance is discharged, there is an advantage that an output signal without delay can be obtained.

〔Effect of the invention〕

As described above, the present invention has a circuit that delays signals so that a large number of buffer circuits operate simultaneously and the discharge current of the load capacitance does not flow into the ground line all at once. This has the effect of avoiding a situation where the operation of other circuits is adversely affected due to instantaneous fluctuations in the ground potential. Furthermore, there is an effect of outputting a signal without delay when charging the load capacitor.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a CMOS buffer according to an embodiment of the present invention, Figs. 2 (A) and (B) are timing diagrams of the load capacitance discharging and charging of the circuit of Fig. 1, and Fig. 3 is a timing chart of the circuit shown in Fig. Second invention
FIG. 4 is a timing diagram of the circuit of FIG. 3. 1.2...CMOS inverter, 3...Input signal control circuit, 4.5.6.7...Delay inverter, 8.
...NAND gate, 9...N channel transistor, 11.12...Input terminal, 13.14...Output terminal, 15...Output terminal. (Al Fig. 8)

Claims (1)

[Claims] In a CMOS buffer circuit having at least a pair of first and second buffer circuits, a logic gate that generates a holding signal by ORing or ANDing an input signal of the first buffer circuit and an output signal thereof; A CMOS buffer circuit comprising: a prohibition circuit that temporarily prohibits an input signal to the second buffer circuit according to a holding signal of the logic gate.