JPH04135315A - Integrated circuit - Google Patents

Abstract

PURPOSE:To reduce noise caused by the state change of the signal of a signal line by detecting the presence/absence of the state change of the signal in wiring and delaying the state change of the signal in the other wiring different from the wiring detecting the state change so as to avoide overlapping of the state change within the range of prescribed time. CONSTITUTION:A signal timing circuit 20 inputs three signals A-C and outputs a signal B2. According to the signal A and the signal C outputting this signal A through an output buffer 10, this signal timing circuit 20 detects the state change of this signal A. When the presence of the state change in the signal A is detected, the state of the signal B2 is stored and held and according to the end of the state change in the signal C while holding the state change of this signal B2, the state of this signal B2 is changed by the signal B. Thus, it is possible to reduce noise caused by a current change to be generated when the state changes of signals in wiring are almost simultaneously generated.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to wiring for transmitting at least two signals inside or outside an integrated circuit, and particularly to an integrated circuit that can effectively reduce noise caused by changes in the state of signals on these signal lines. Regarding.

[Conventional technology]

Conventionally, in an integrated circuit or an electronic circuit using an integrated circuit, when the state of a signal on a signal line in the integrated circuit or in such an electronic circuit changes, the power supply inside such an integrated circuit or electronic circuit is It is known that noise voltage is generated on the power supply line or ground line for supplying the power. This means that when the state of a signal input to a logic element that constitutes such an integrated circuit or electronic circuit changes, the state of such logic element or the state of the output signal of such logic element changes. This is because the current consumption of such a logic element changes rapidly due to the change in the current consumption. Usually, the power supply voltage supplied to an integrated circuit or an electronic circuit using such an integrated circuit is maintained at a predetermined power supply voltage. However, if there is a sudden change in the current consumption of the logic elements that make up the integrated circuit or electronic circuit as described above, extremely short-term fluctuations in the power supply voltage (noise voltage superimposed on the power supply voltage) may occur. ) will occur. This is caused by electrical resistance distributed in the power supply line and ground line. If a noise voltage is generated between the power supply line and the ground line when the state of the signal on the signal line changes and is superimposed on the power supply voltage, this power supply voltage is used to determine the judgment value (threshold voltage or comparison voltage). There is a problem in that logic elements and the like that obtain this result in malfunction. Also, if noise voltage is induced in the signal of the signal line wired near the power supply line or ground line,
There is a problem in that a malfunction such as inverting a logic circuit, such as a flip-flop, to which the signal from this signal line is input may occur. In particular, when changes in the signal states of multiple signal lines occur almost simultaneously in multiple signal lines within an integrated circuit or in an electronic circuit using an integrated circuit, rapid changes in current consumption may occur. As a result, a problem arises in that a larger noise voltage is superimposed on the power supply voltage. Various methods have been proposed to reduce such noise voltage superimposed on the power supply voltage. For example, by increasing the rise time and fall time of the signal on the signal line, the state changes of the logic elements to which this signal is input are made more rapid, and the current consumption of these elements does not change suddenly. There is a way to do this. One way to lengthen the rise time and fall time of such a signal on a signal line is to add a series resistor to the output section that outputs this signal to reduce the signal current of this signal. There is a method of lengthening the rise time and fall time of this signal by suppressing the peak current of the driver transistor that outputs the signal and reducing the peak current of the signal that occurs when the state of the signal changes. In addition, in order to reduce the noise voltage that is superimposed on the power supply voltage due to sudden changes in the current consumption of multiple logic elements due to changes in the state of signals on multiple signal lines,
Another method has been used to reduce the number of logic elements that operate almost simultaneously. For example, if multiple signals on multiple signal lines change almost simultaneously inside an integrated circuit or in an electronic circuit using an integrated circuit, when these simultaneous changes occur, A method has been used in which the state change timing of some of the plurality of signals on the signal line is delayed, thereby reducing the number of logic elements whose states change simultaneously.

[Problem to be achieved by the invention]

However, as mentioned above, in order to reduce the noise voltage superimposed on the power supply voltage, if the rise time and fall time when the signal state of the signal line changes is lengthened, the operating speed of the electronic circuit will decrease. problems and a reduction in the drive ability of the signal line. In addition, when some signals of multiple signals on multiple signal lines whose states change almost simultaneously are delayed, the delay time at this time is enough to ensure the timing of the state changes of these multiple signals. Since the time must be long enough to allow the shift, such a long signal delay causes a problem of slowing down the operating speed of the electronic circuit. The present invention was made in order to solve the above-mentioned conventional problems. without delaying the signal.
without deteriorating usage conditions such as signal drive ability.
It is possible to effectively reduce noise caused by current changes in logic elements downstream of these wirings whose states change according to these signals, which occurs when the state changes of the signals on these wirings occur almost simultaneously. The purpose is to provide integrated circuits.

[Means to achieve the task]

The present invention provides an integrated circuit that includes at least two wires for transmitting signals inside the integrated circuit or outside the integrated circuit, and detects whether or not there is a change in the state of a signal in at least one of the wires. The above-mentioned problem can be solved by providing a state change detection circuit for detecting a state change, and when detecting a state change, delaying the state changes of signals of other wirings among the wirings so that they do not overlap within a predetermined time range. It is something to be achieved. Furthermore, the present invention delays the state changes within a predetermined time range so that they do not overlap, only when the state after the state change of each wiring whose state is changing is biased toward one state. It accomplishes the task.

[Effect]

In the present invention, it is possible to reduce noise caused by changes in current consumption when the state changes of signals of multiple wirings inside or outside the integrated circuit occur almost simultaneously. The state changes of these multiple signals do not overlap within a predetermined time range (this predetermined time may be almost zero) by using the minimum necessary delay time without increasing the time or fall time. I'm trying to shift it. In particular, in the present invention, the presence or absence of a change in the state of a signal of at least one of the plurality of wires is detected, and after detecting that the state has changed and the state change has been completed, the signal is approximately equal to that of the signal. The states of the signals of other wirings that change at the same time or with a slight delay are made to change. The present invention has the advantage of delaying some of the signals of the plurality of wirings in order to reduce the noise superimposed on the power supply voltage when the state changes of the plurality of signals occur almost simultaneously. Similar to one of the examples. However, the signal delay time for noise reduction according to the present invention is much smaller than the signal delay time of this conventional example. That is, in this conventional example, the delay time of the signal between the plurality of wirings is determined according to the worst case of the signal transmission time, which differs due to variations in each integrated circuit or each element in the integrated circuit, differences in operating conditions, etc. was. The difference in signal transmission time between each integrated circuit or each element in an integrated circuit is
It is relatively large. Therefore, the worst value of signal transmission time in an integrated circuit is much larger than the standard value. Therefore, the delay time for noise reduction in this conventional example has become a large value. However, in the present invention, in order to reduce noise when state changes of a plurality of signals occur almost simultaneously, the presence or absence of a state change of some of these signals is detected, and the presence or absence of a state change of a part of these signals is detected. Since the signal states of other wirings change upon termination, the delay time that occurs at this time can be suppressed to an extremely small amount. In addition, in the present invention, if the delay so that the state changes do not overlap within a predetermined time range is performed only when the state after the state change of each wiring whose state is changing is biased to one state, Since such delays are performed less frequently, the average signal delay time can be reduced.

【Example】

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a logic circuit diagram of a first embodiment of the present invention. In this FIG. 1, a signal A and a signal B of an internal circuit 30 are shown.
are output as signals A1 and B1, respectively, via the output buffer 10. If the states of these signals AI and B1 change at the same time, the total value of changes in current consumption becomes large, and a large noise voltage occurs in the power supply voltage. The signal timing circuit 20 inputs three signals A to C and outputs a signal B2. The signal timing circuit 20 first detects a change in the state of the signal A using the signal A and the signal C from which the signal A is output via the output buffer 10. That is, it detects a short-term state difference between signal A and signal C that occurs when signal A changes state due to the signal transmission time of output buffer 10. Further, the signal timing circuit 20 detects a change in the state of the signal A, and also determines the state of the output signal B2 according to the states of the signal A and the signal B, respectively. FIG. 2 is a graph of signal A and signal B2 in the first embodiment of the present invention described above. In FIG. 2, the signal A changes from the L state to the H state at time 8, and from the H state to the L state at time 9. Further, the signal B changes its state from the L state to the H state at time C, and changes from the H state to the L state at time 1. Also, according to signal A, signal C changes from the L state to the H state at time 5.
The state changes from the H state to the L state at one time. The signal timing circuit 20 of FIG. 1 described above detects the state change of the signal A by detecting the 11th hour and the 12th hour shown in FIG.
It is possible to detect the completion of the state change of signal A between time i and time i (completion of the state change of signal C). Further, when a change in the state of the signal A is detected, the signal timing circuit 20 stores and holds the state of the signal B2, and suspends the change in the state of the signal B2 at times t1 and t2). , the end of the state change of signal C (time b
, 1), the state of this signal B2 (solid line A) is changed to signal B
(time d and time k)
. Note that the broken line B in FIG. 2 is a graph of the signal B2 obtained by delaying the signal B by a conventional delay time with sufficient margin. Times d1 and 1 of this broken line B correspond, respectively, to times d and k of the solid line A, which is the graph of the signal B2 according to the invention, and are very delayed. In addition, in the present invention, such holding of signal B2 (holding or delaying the state change of signal B2 with respect to the state change of signal B) is performed when the state changes of signal A and signal B occur at the same time. This may be performed only when the signal A and signal B are in the same state after the state change. Fig. 3 shows the signal A when done in this way,
5 is a diagram showing the relationship between signal B and signal B2 whose state changes according to the state change of signal B. FIG. Note that when the target signals are not two signals but more than two signals as in the first embodiment of the present invention, the state changes are delayed so that they do not overlap within a predetermined time range. This may be performed only when the state of each wiring whose state is changed is favorable to one state after the state change. For example, if there are six target signals, three of them will be in the H state after the state change, and if the other three signals will be in the L state after the state change, these signals will be in the H state after the state change. If delay is not performed so that the state changes of the signals do not overlap, and on the other hand, 4 of these 6 signals become H state after the state change, and 2 signals become the state after the state change. Alternatively, the signals that change to the H state at the same time may be delayed so that they do not overlap. Further, in FIG. 1, the time range in which the state changes of the signal A1 and the signal B2 do not overlap is determined according to the signal transmission time of the output buffer. If it is necessary to further widen this time range, a signal delay means may be attached to the Y portion in FIG. This may be a buffer gate or the like. FIG. 4 is a logic circuit diagram showing an example of the signal timing circuit of the first embodiment of the present invention described above. In this FIG. 4, reference numeral 20. A, B, B2, C are
These are the same as those with the same reference numerals in FIG. 1 described above. In FIG. 4, the signal timing circuit 20 is composed of one exclusive OR 12 and a D-type catch 14. Signals A and C are input to this exclusive OR 12, and the output of this exclusive OR is a D-type switch 1.
It is input to input CK of No. 4. Therefore, when the state of signal A changes, that is, when a difference occurs between the states of signal A and signal C that occur over time, the output of exclusive OR 12 becomes H state, and this H state becomes D-type switch 14. is input to the input CK of Further, the signal B is input to the input of the D-type switch 14. This D-type switch 14 maintains the state of the output OUT when the input CK is in the H state, and when the input CK becomes the L state, the state of the output OUT changes according to the state of the input. Therefore, when a change in the state of signal A is detected by exclusive OR 12, the state of signal B2 is held, and the state of signal B2 is determined according to signal B after the state of signal C changes. FIG. 5 is a logic circuit diagram showing a second embodiment of the present invention. In FIG. 5, the signal A output from the internal circuit 30 is input to the input of the D-type switch 14, and the output from the output OUT of the D-type switch 14 is output from the output buffer 10.
The signal is outputted as a signal A1 via the signal A1. Also, the signal B of the internal circuit 30 is sent to another D-type switch 1.
4, and the output O of this D-type U-y-chie 4
The output from the UT is output via another output buffer 10 as signal B1. The input CK of the D-type switch 14 inputting the signal A is as follows.
The output of exclusive OR 12 is input, and the two inputs of exclusive OR 12 are input with signal B and signal B1. Therefore, this exclusive OR detects a change in the state of signal B and outputs this result to input CK of D-type switch 14. In addition, the input CK of the D-type switch 14 to which the signal B is input
is connected to the output of another exclusive OR 12. A signal A and a signal A1 are input to two inputs of this exclusive OR 12, so that this exclusive OR 12 can detect the presence or absence of a change in the state of the signal A. Therefore, according to the second embodiment of the present invention, the state of the signal B changes during the period from when the state change occurs in the signal A until the completion of the state change of the signal A1 whose state changes according to the signal A. When this occurs, the change in the state of the signal B1, which changes according to the state of the signal B, is suspended until the change in the state of the signal A1 is completed. Furthermore, if the state of signal A changes during the period from when the state of signal B changes until the completion of the state change of signal B1 that changes according to the state of signal B, this signal A
The change in the state of the signal A1, which changes according to the state of the signal A1, is suspended until the change in the state of the signal B1 is completed. Therefore, according to the second embodiment of the present invention, even if signal A and signal B overlap at almost the same time, no matter which of these two signals A and B comes first, signal A1 Signal overlap with signal B1 can be prevented with the minimum necessary delay time.

【Effect of the invention】

As explained above, according to the present invention, in an integrated circuit including at least two or more wiring lines for transmitting signals inside the integrated circuit or outside the integrated circuit, the signals can be transmitted without unnecessarily delaying the signals. It has the excellent effect of effectively reducing noise caused by current changes that occur when signal state changes in these wirings occur almost simultaneously, without deteriorating usage conditions such as signal drive ability. Obtainable.

[Brief explanation of drawings]

FIG. 1 is a logic circuit diagram of the first embodiment of the present invention, FIG. 2 is a graph of the signal A, signal B, and signal B2 according to the elapsed time of the first embodiment of the present invention, and FIG. is a diagram showing the relationship between the state changes of signal A, signal B, and signal B2 in the first embodiment of the present invention, and FIG.
FIG. 5 is a logic circuit diagram of an example of the signal timing circuit of the first embodiment of the present invention. FIG. 5 is a logic circuit diagram of the second embodiment of the present invention. 10... Output buffer, 12... Exclusive OR, 14... D type catch, 20... Signal timing circuit, A to C, A1, B1, B2... Signal, a to d, dl,
O, h, i, k, kl--time, tl,
t2... time.

Claims (2)

[Claims] (1) In an integrated circuit that includes at least two or more wiring lines for transmitting signals inside the integrated circuit or outside the integrated circuit, detecting the presence or absence of a change in the state of a signal in at least one of the wiring lines. an integrated circuit comprising: a state change detection circuit; when a state change is detected, the integrated circuit delays state changes of signals on other wirings among the wirings so that they do not overlap within a predetermined time range. . (2) Claim 1, characterized in that the delay so that the state changes do not overlap within a predetermined time range is performed only when the state of each wiring whose state is changing after the state change is biased toward one state. integrated circuit.