JP2686357B2 - Integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Industrial applications]

The present invention relates to a wiring for transmitting at least two or more signals inside or outside an integrated circuit, and in particular, an integrated circuit capable of effectively reducing noise due to a change in a signal state of these signal lines. Regarding

[Prior art]

Conventionally, inside an integrated circuit, or in an electronic circuit using the integrated circuit, inside the integrated circuit, or
It is known that a noise voltage is generated on a power supply line or a ground line for supplying power in such an integrated circuit or an electronic circuit when the state of a signal on a signal line in such an electronic circuit changes. This is because, in a logic element that constitutes such an integrated circuit or electronic circuit, when the state of the signal input to this logic element changes, the state of such a logic element or the state of the output signal of such a logic element is changed. This is because the current consumption of such a logic element changes abruptly. Usually, the power supply voltage supplied to an integrated circuit or an electronic circuit using such an integrated circuit is kept at a predetermined power supply voltage. However, when there is a sudden change in the current consumption of the logic elements that make up the integrated circuit or electronic circuit as described above, fluctuations in the power supply voltage for a very short time (noise voltage that is superimposed on the power supply voltage ) Will occur. This is caused by the electric resistance distributed on the power supply line or the ground line that supplies power. When a noise voltage is generated between the power supply line and the ground line due to superimposition on the power supply voltage when the state of the signal on the signal line changes, the judgment value (threshold voltage or comparison voltage) is determined using this power supply voltage. There is a problem that a logic element or the like that obtains a malfunction may cause a malfunction. Also, if noise voltage is induced in the signal of the signal line that is wired near such a power line or ground line, the logic circuit that inputs the signal of this signal line, such as a flip-flop, is inverted. There is a problem in that there is a possibility that a malfunction such as an accident may occur. In particular, when a plurality of signal lines in an integrated circuit or in an electronic circuit using the integrated circuit have a signal state change of the plurality of signal lines almost at the same time, a rapid change in current consumption is concentrated. This causes a problem that a larger noise voltage is superimposed on the power supply voltage. Various methods have been proposed to reduce the noise voltage that is superimposed on the power supply voltage. For example, by lengthening the rise time and the fall signal of the signal on the signal line, the state change of the logic element inputting this signal is made gradual so that the change of the current consumption of these elements does not change suddenly. There is a method. As a method of prolonging the rise time and fall time of the signal on such a signal line, there is a method of adding a series resistor to the output portion for outputting this signal to reduce the signal current of this signal. Further, there is a method of suppressing the peak current of a driver transistor that outputs a signal and reducing the peak current of the signal generated when the state of the signal changes to prolong the rise time and fall time of this signal. Further, in order to reduce the noise voltage that is superimposed on the power supply voltage due to the abrupt change of the current consumption of the plurality of logic elements accompanying the change of the signal states of the plurality of signal lines, they are operated almost at the same time. A method of reducing the number of logic elements is also used. For example, when a plurality of signals of a plurality of signal lines are changed substantially at the same time inside the integrated circuit or in an electronic circuit using the integrated circuit, the plurality of signals simultaneously changing at the same time are changed. A method of delaying the state change timing of a part of a plurality of signals on a signal line to reduce the number of logic elements whose states change simultaneously is performed.

[Problems to be solved by the invention]

However, as described above, when the rise time and the fall time at the time of changing the state of the signal on the signal line are increased in order to reduce the noise voltage superimposed on the power supply voltage, it is said that the operating speed of the electronic circuit decreases. There arises a problem and a problem that the drive capability of the signal line is deteriorated. In addition, when a part of the plurality of signals of the plurality of signal lines in which the state changes occur at substantially the same time is delayed, the delay time at this time surely shifts the timing of the state change of these plurality of signals. Since it has to be a sufficient length of time, the delay of the signal of such a sufficient length causes a problem that the operation speed of the electronic circuit is lowered. The present invention has been made to solve the above-mentioned conventional problems, and in an integrated circuit including wirings for transmitting at least two or more signals inside or outside the integrated circuit, it is possible to eliminate these problems. Due to the current change of the logic element that changes state according to these signals, which occurs when the signal state changes of these wirings occur almost at the same time without delaying the signal and without deteriorating the usage conditions such as the signal drive capability. An object of the present invention is to provide an integrated circuit capable of effectively reducing generated noise.

[Means for achieving the object]

The present invention relates to an integrated circuit including wirings for transmitting at least two signals inside or outside the integrated circuit, the presence / absence of a signal state change of at least a pair of wirings among the wirings, A state change detection circuit that detects the logical state of each signal and the logical state of the input of the gate circuit that outputs the signal independently of each other based on the result of the exclusive OR operation, and the state change of one signal When the presence is detected, the state change of the other signal is delayed according to the result of the exclusive OR operation of the one signal so that the state change of the signal of the pair of wirings does not overlap each other within a predetermined time range. The above-mentioned problems can be achieved by providing a circuit for performing the above.

[Action]

In the present invention, it is necessary to reduce the noise caused by the change in current consumption when the signal state changes of a plurality of wirings inside the integrated circuit or outside the integrated circuit occur almost simultaneously. Do not increase the time or fall time, and make sure that the state changes of these multiple signals do not overlap within the range of the specified time (this specified time may be almost zero) with the minimum required delay time. I am trying to shift it. In particular, in the present invention, after detecting the presence or absence of the state change of the signal of at least one of the plurality of wirings and detecting the state change and the end of this state change, the signal is almost The signal states of other wirings whose states change at the same time or with some delay are changed.
In the present invention, first, by providing a state change detection circuit, the presence or absence of the state change of the signal of at least a pair of wirings among the wirings is determined by the logical state of each signal and the input logic of the gate circuit that outputs the signal. The states are detected independently of each other according to the result of the exclusive OR operation with the state. Further, a circuit for delaying the state change is provided, and when it is detected that the state of one of the signals is changed, the state of one of the signals is changed so that the state changes of the signals of the pair of wirings do not overlap each other within a predetermined time range. The state change of the other signal is delayed according to the result of the exclusive OR operation. With such a configuration, the signal delay time in the present invention is suppressed. The point of delaying a part of the signals of the plurality of wirings in order to reduce the noise superimposed on the power supply voltage when the state changes of the plurality of signals occur almost at the same time in the present invention is the same as the above-mentioned conventional method. Similar to one of the examples. However, the signal delay time for noise reduction of the present invention is much shorter than the signal delay time of this conventional example. That is, in this conventional example, the signal delay time between a plurality of wirings is determined according to the worst case of different signal transmission times due to variations in each integrated circuit or each element in the integrated circuit and differences in operating conditions. Was there. The difference in signal transmission time for each integrated circuit or each element in the integrated circuit is relatively large. Therefore, the worst value of the signal transmission time in the integrated circuit is much larger than the standard value. Therefore, the delay time for noise reduction in this conventional example has become a large value. However, in the present invention, in order to reduce noise when the state changes of a plurality of signals occur almost at the same time, the presence or absence of a state change of some of the plurality of signals is detected, and the state change of these signals is detected. Since the signal states of the other wirings are changed by the termination, the delay time generated at this time can be suppressed to an extremely small amount.

【Example】

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a logic circuit diagram of the first embodiment of the present invention. This embodiment shows an example of the state change detection and state change delay of another signal based on the state change detection according to the present invention with a limited configuration. That is, regarding the simultaneous state change of the signal A and the signal B of the pair of wirings, the simultaneous change is completely simultaneous, or as shown in the time chart of FIG.
It is premised that the signal A is slightly earlier than the signal B. Except for this assumption, the noise reduction effect is limited. For purposes of illustration, the present invention has not been fully embodied in this example. This first
In the figure, the signal A and the signal B of the internal circuit 30 are output as the signals A1 and B1 via the output buffer 10, respectively. If the states of these signals A1 and B1 change at the same time,
The total value of changes in the consumed current becomes large, and a large noise voltage is generated in the power supply voltage. The signal timing circuit 20 inputs three signals A to C and outputs a signal B2. The signal timing circuit 20 first detects a change in the state of the signal A based on the signal A and the signal C output from the signal A via the output buffer 10. That is, the difference in the short-time state between the signal A and the signal C, which occurs when the state of the signal A changes due to the signal transmission time of the output buffer 10, is detected. Further, the signal timing circuit 20 detects the state change of the signal A and determines the state of the signal B2 to be output according to the respective states of the signal A and the signal B. FIG. 2 shows the signal A in the first embodiment of the present invention described above.
And a signal B2. In FIG. 2, the signal A changes from the L state to the H state at time a.
The state changes to the state, and the state changes from the H state to the L state at time g. Further, the signal B changes from the L state to the H state at time c, and changes from the H state to the L state in the h state. Further, the signal C changes from the L state to the H state at time b according to the signal A, and changes from the H state to the L state at time i. The signal timing circuit 20 of FIG. 1 described above detects a change in the state of the signal A and the time b and the time by detecting the t1 time and the t2 time shown in FIG. 2 by the input signals A and C. Completion of the state change of the signal A with i (completion of the state change of the signal C) can be detected. Further, when it is detected that the state of the signal A has changed, the signal timing circuit 20 stores, for example, the state of the signal B2 and holds the state change of the signal B2 (time t1, t2). ), The state of the signal B2 (solid line A) is changed by the signal B when the state change of the signal C ends (time b, i) (time d and time k). The broken line B in FIG. 2 is a graph of the signal B2 obtained by delaying the signal B by the delay time of the conventional sufficient margin. The times d1 and k1 on the broken line B correspond to the times d and k on the solid line A, which is a graph of the signal B2 according to the present invention, respectively, and are very delayed. Note that the holding of the signal B2 (holding the state change of the signal B2 or delaying the state change of the signal B2 with respect to the state change of the signal B) of the present invention is performed at the same time by the state change of the signal A and the signal B. It may be performed only when the signal A and the signal B are generated and the states after the state change are the same. FIG. 3 is a diagram showing the relationship between the signal A, the signal B, and the signal B2 whose state is changed in accordance with the state change of the signal B in this case. When the signals of interest are not two signals but more signals as in the first embodiment of the present invention, the state changes are delayed so that they do not overlap within a predetermined time range. This may be performed only when the state after the state change of each wiring is biased to one state. For example, if the number of target signals is 6, three of these signals are in the H state after the state change, and the other three signals are in the L state after the state change. Delay is not performed so that the signal state changes do not overlap, while four of these six signals are in the H state after the state change, and two signals are in the L state after the state change. Alternatively, signals that change to the H state at the same time may be delayed so as not to overlap with each other. In this sense, applying the present invention in consideration of the state after the state change for a plurality of signals in this way can be said to be an extension of the idea described above with reference to FIG. Further, in FIG. 1, the time range in which the state changes of the signal A1 and the signal B2 are not overlapped is determined according to the signal transmission time of the output buffer. When it is necessary to further widen this time range, a signal delay means may be attached to the Y portion of FIG. This may be a buffer gate or the like. FIG. 4 is a logic circuit diagram showing an example of the signal timing circuit according to the first embodiment of the present invention. In FIG. 4, reference numerals 20, A, B, B2 and C are the same as those having the same reference numerals in FIG. In FIG. 4, the signal timing circuit 20 is composed of one exclusive OR 12 and a D-type latch 14. Signals A and C are input to this exclusive OR 12, and the output of this exclusive OR is a D-type latch 14
Input to CK. Therefore, when the state of signal A changes,
That is, when a temporary difference in the states of the signal A and the signal C occurs, the output of the exclusive OR 12 becomes the H state, and this H state is input to the input CK of the D-type latch 14. Further, the signal B is input to the input D of the D-type latch 14. This D-type latch 14 outputs when the input CK is in the H state.
When the state of OUT is held and this input CK becomes L state,
The state of the output OUT changes according to the state of the input D. Therefore, when the exclusive OR 12 detects the state change of the signal A, the state of the signal B2 is held, and after the state change of the signal C, the state of the signal B2 is set according to the signal B. FIG. 5 is a logic circuit diagram showing a second embodiment of the present invention. In FIG. 5, the signal A output from the internal circuit 30 is input to the input D of the D-type latch 14, and the output from the output OUT of the D-type latch 14 is output as the signal A1 via the output buffer 10. Is output. The signal B of the internal circuit 30 is the other D-type latch 14
Of the D-type latch 14 and the output from the output OUT of the D-type latch 14 is output as a signal B1 via another output buffer 10. The output of the exclusive OR 12 is input to the input CK of the D-type latch 14 receiving the signal A, and the signals B and B1 are input to the two inputs of the exclusive OR 12. Therefore, this exclusive OR detects the state change of the signal B and outputs the result to the input CK of the D-type latch 14. Further, the output of the other exclusive OR 12 is connected to the input CK of the D-type latch 14 to which the signal B is input. The signal A and the signal A1 are input to the two inputs of the exclusive OR 12, so that the exclusive OR 12 can detect whether or not the state of the signal A has changed. Therefore, according to the second embodiment of the present invention, the state of the signal B changes in the period from the state change of the signal A to the completion of the state change of the signal A1 which changes the state according to the signal A. In this case, the change of the state of the signal B1 which changes according to the state of the signal B is held until the change of the state of the signal A1 is completed. If the state of the signal A changes during the period from the state of the signal B changing to the completion of the state change of the signal B1 changing according to the state of the signal B, the signal A
The state of signal A1 that changes according to the state of
It is held until the completion of the state change of. Therefore, according to the second embodiment of the present invention, even when the signal A and the signal B overlap at the same time, whichever of the two signals A and B comes first, the signal A
Overlapping of the signals of A1 and B1 can be prevented with a minimum required delay time.

【The invention's effect】

As described above, according to the present invention, in an integrated circuit including wiring for transmitting at least two or more signals inside the integrated circuit or outside the integrated circuit, without delaying these signals unnecessarily, It is possible to effectively reduce the noise generated by the current change that occurs when the signal state changes of these wirings occur almost at the same time without deteriorating the usage conditions such as the signal drive capability. Obtainable.

[Brief description of the drawings]

FIG. 1 is a logic circuit diagram of a first embodiment of the present invention, and FIG. 2 is a signal A and a signal B of the first embodiment of the present invention.
And a graph according to the elapsed time of the signal B2, FIG. 3 is a diagram showing the relationship of the state changes of the signal A, the signal B and the signal B2 of the first embodiment of the present invention, and FIG. FIG. 5 is a logic circuit diagram of an example of the signal timing circuit of the first embodiment of the present invention, and FIG. 5 is a logic circuit diagram of the second embodiment of the present invention. 10 ... Output buffer, 12 ... Exclusive OR, 14 ... D-type latch, 20 ... Signal timing circuit, A to C, A1, B1, B2 ... Signal, a to d, d1, g, h, i , K, k1 …… time, t1, t2 …… time.

Claims (1)

(57) [Claims] 1. An integrated circuit including wirings for transmitting at least two signals inside or outside the integrated circuit, wherein at least a pair of wirings among the wirings is checked for presence / absence of signal state change. , A state change detection circuit that detects the logical state of each signal and the logical state of the input of the gate circuit that outputs the signal independently of each other by the result of the exclusive OR operation, and the state of one signal When a change is detected, the state change of the signal of one of the wirings is changed according to the result of the exclusive OR operation of the other signal so that the state change of the signal of the pair of wirings does not overlap each other within a predetermined time range. An integrated circuit comprising a delay circuit.