JPH0611103B2 - Output circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit, and more particularly to an output control circuit that avoids simultaneous output changes of a plurality of output terminals.

[Conventional technology]

Generally, in an integrated circuit having a plurality of output terminals, signals may appear at several output terminals at the same time depending on the timing of the internal circuit. At that time, a large transient current concentrates and causes noise.

In order to avoid this simultaneous output change, the conventional output circuit
As shown in FIG. 5 as an example, a delay circuit 1 having a different delay amount immediately before output with respect to outputs that are considered to change simultaneously
1 and 12 are inserted to avoid simultaneous output changes due to the delay difference.

[Problems to be solved by the invention]

The above-mentioned conventional output circuit has a problem that it is necessary to check the outputs which are simultaneously changed in advance and install a delay circuit corresponding to them.

Further, when the output transient period, that is, the period during which the transient current passes, changes depending on the load capacitance connected to the output circuit, there is a problem in that the output load capacitance must also be considered.

An object of the present invention is that it is not necessary to individually provide a delay circuit in consideration of the timing of an internal circuit, and it is possible to prevent simultaneous output changes and prevent noise generation regardless of the conditions of the output side circuit. It is to provide an output circuit.

[Means for solving problems]

The output circuit of the present invention includes a first transfer gate having an input end connected to a first input terminal, an input end connected to an output end of the first transfer gate, and an output end connected to a first output terminal. A first buffer gate connected to the first buffer gate; a second buffer gate having an input terminal connected to the first output terminal; an input terminal connected to an output terminal of the second buffer gate; A second transfer gate connected to the output terminal of the second transfer gate, and the first transfer gate and the second transfer gate using a signal from a second input terminal.
And a latch circuit including a control circuit for controlling conduction and non-conduction with the transfer gate in an opposite phase, and an exclusive OR of the signal from the first input terminal and the signal from the second buffer gate. And a plurality of output control circuits including an output transient period detection circuit for outputting from the second output terminal, the second output terminal of the output control circuit of the front stage and the second input terminal of the output control circuit of the rear stage. The first output of each output control circuit is connected by applying the ground potential to the second input terminal of the first output control circuit and inputting an external signal to the first input terminal of each output control circuit. It is characterized in that the output signal is taken out from the terminal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The embodiment shown in FIG. 1 has two output control circuits 10 ₁ and 10 _1.
It consists of _two . Each of the two output control circuits ₁₀ 1/10 _2, the transfer gates 3 and 4 and the buffer gate 5,
6, a latch circuit 1 including an inverter 2 as a control circuit, and an exclusive OR circuit 7 as an output transient detection circuit
And a second output terminal C ₁ of the output control circuit 10 ₁ of the _first stage and a second output terminal C 2 of the output control circuit 10 ₂ of the second stage.
Input terminal B _{2 of} is connected. Output control circuit 1 of the first stage
The second input terminal B ₁ of 0 ₁ is grounded.

Here, the operation of the two output control circuit will be described with reference to the time diagram of FIG. 2 takes the output control circuit 10 ₂ as an example. When the input from the _second input terminal B ₂ has the logical value “1”, the transfer gate 3 becomes non-conductive and the transfer gate 4 becomes conductive, whereby the latch circuit 1
Becomes a latched state, and conversely, when the signal from the input terminal B ₂ has a logical value of “0”, the transfer gate 3 becomes conductive, the transfer gate 4 becomes non-conductive, and the latch circuit 1 becomes a signal passing state. Further, when the first output terminal O ₂ is in a transient state, the output transient state detection signal is output from the exclusive OR circuit 7 to the second output terminal C ₂ .

Next, FIG. 3 is a time chart for explaining the operation of the present embodiment shown in FIG. Referring to FIG. 3, when the output control circuit 10 _{1 in} FIG. ₁ is in a transient state, the output terminal C ₁
Output transient state detection signal is input to the input terminal B ₂ of the output control circuit 10 from _2, when the input of the output transient state detection signal output control circuit 10 ₂ is latched, as a result, the output terminal O ₁ and the output terminal O The output from ₂ is prohibited from changing simultaneously. Therefore, the generation of noise is prevented without providing a delay circuit and regardless of the conditions of the output side circuit.

Furthermore, even if the number of output control circuits is increased to three or more, the simultaneous simultaneous output change can be avoided in the same manner, and noise is prevented.

〔The invention's effect〕

As described above, the output circuit of the present invention prohibits all other outputs from changing when a certain one output is in a transient state, so that the delay is individually delayed in consideration of the timing of the internal circuit. No need for a circuit, and
Since it is possible to avoid simultaneous changes in the output regardless of the conditions of the output side circuit, it is possible to prevent the generation of noise.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
Time diagram for explaining the operation of the output control circuit 10 ₂ shown in FIG., FIG. 3 is a time chart for explaining the operation of the embodiment shown in FIG. 1, FIG. 4 is an example of a conventional output circuit It is a block diagram. 1 ... Latch circuit, 2 ... Inverter, 3, 4 ... Transfer gate, 5, 6 ... Buffer gate, 7 ... Exclusive OR circuit, 10 ₁ , 10 ₂ ... Output control circuit, 11, 12 ... Delay circuit, A ₁ , A ₂ , B ₁ , B ₂ ... Input terminals, C ₁ , C
₂ , O ₁ , O ₂ ... Output terminals.

Claims (1)

[Claims] 1. A first input terminal connected to a first input terminal.
And a first buffer gate having an input end connected to an output end of the first transfer gate and an output end connected to a first output terminal, and an input end of the first transfer gate.
A second buffer gate connected to the output terminal, and a second transfer gate having an input terminal connected to the output terminal of the second buffer gate and an output terminal connected to the output terminal of the first transfer gate. A latch circuit comprising a control circuit for controlling conduction and non-conduction between the first transfer gate and the second transfer gate in a reverse phase by a signal from a second input terminal, and the first input An output control circuit including a plurality of output control circuits including an output transition period detection circuit that outputs an exclusive OR of the signal from the terminal and the signal from the second buffer gate and outputs the result from the second output terminal. The second output terminal of the output control circuit of the latter stage is connected to the second input terminal of the output control circuit of the first stage, and the ground potential is applied to the second input terminal of the output control circuit of the first stage. Input terminal Output circuit, characterized in that inputs a signal from the outside and configured to retrieve the output signal from the first output terminal of the respective output control circuits.