JPS62176324A - Output control circuit - Google Patents

Abstract

PURPOSE:To prevent noise from being generated by inhibiting the change of all other outputs at the time of one output is kept in the transient state. CONSTITUTION:When an input from the 2nd input terminal B is logical 1 a transfer gate 3 is nonconductive, a transfer gate 4 is conductive, a latch circuit 1 is latched, and when a signal from the input terminal B is logical 0 conversely, the transfer gate 3 is conductive, the transfer gate 4 is nonconductive and the latch circuit 1 is in the signal passing state. When the 1st output terminal 0 is in the transient state, on output transient state detection signal is outputted from an exclusive OR circuit 7 to the 2nd output terminal C. When 2-stage of output control circuits are provided, the output terminal C of the 1st stage output control circuit and the input terminal B of the 2nd stage output control circuit are connected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output control circuit, and more particularly to an output control circuit that avoids simultaneous changes in the outputs of a plurality of output terminals.

[Conventional technology]

Generally, in an integrated circuit having multiple output terminals, signals may appear simultaneously at several output terminals depending on the timing of the internal circuit, but in this case, large transient currents concentrate and cause noise generation.

In order to avoid this simultaneous change in output, a conventional output control circuit uses delay circuits 11.1, 11.1, and 11.22, which have different delay amounts immediately before the outputs for outputs that are expected to change simultaneously, as shown in FIG. 12 was inserted to avoid simultaneous output changes due to the delay difference.

1. Problems to be Solved by the Invention The above-described conventional output control circuit has a problem in that simultaneously changing outputs must be checked in advance and a corresponding delay circuit must be installed.

Furthermore, if the output transient period, that is, the period during which a transient current passes, changes depending on the load capacitance connected to the output circuit, there is a problem in that the output load capacitance must also be taken into consideration.

An object of the present invention is to avoid the need to provide a separate delay circuit in consideration of the timing of the internal circuit, and to avoid simultaneous changes in the output and prevent the generation of noise regardless of the conditions of the output side circuit. The objective is to provide an output control circuit that can

Means for Solving Problems] The output control circuit of the present invention includes a first transfer gate whose input terminal is connected to a first input terminal.

a first buffer gate whose input terminal is connected to the first transfer gate and whose output terminal is connected to the first output terminal; and a second buffer gate whose input terminal is connected to the first output terminal. a second transfer gate 1- whose input terminal is connected to the output terminal of the second buffer gate and whose output terminal is connected to the output terminal of the first transfer gate; said first at the signal
a control circuit that controls conduction and non-conduction between the transfer gate and the second transfer gate in an antiphase manner; a signal from the first input terminal and the second buffer gate; and an output transient period detection circuit that performs an exclusive OR with a signal from the output terminal and outputs the result from the second output terminal.

[Example 1 Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.

The embodiment shown in FIG. 1 is a transfer gate 3.

4, a buffer gate 5.6, an inverter 2 as a control circuit, and an exclusive OR circuit 7 as an output transition period detection circuit.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to the time chart shown in FIG.

When the input from the second input terminal B is a logical value "1", the transfer gate 3 becomes non-conductive and the transfer gates 1 to 4 become conductive, so that the latch circuit 1 enters the latched state, and conversely, the latch circuit 1 enters the latched state. When the signal from is logical value “0”,
Transfer gate 3 becomes conductive, transfer gate 4 becomes non-conductive, and latch circuit 1 enters a signal passing state.

Further, when the first output terminal 0 is in a transient state, an output transient state detection signal is outputted from the exclusive OR circuit 7 to the second output terminal C.

FIG. 3 is a block diagram of a second embodiment of the invention.

The embodiment shown in FIG. 3 shows a case where the output control circuit of the first embodiment described above has two stages.

The second output terminal C. of the first stage output control circuit 101. and 2
The second input terminal Bz of the output control circuit 102 in the second stage is connected.

FIG. 4 is a time chart for explaining the operation of the embodiment shown in FIG. 3.

When the output control circuit 10K is in a transient state, the output terminal C1
The output transient state detection signal is input to the input terminal B2 of the output control circuit 10□, and when the output transient state detection signal is input, the output control circuit 102 is latched. Outputs are prohibited from changing simultaneously. Therefore, generation of noise is prevented without providing a delay circuit and regardless of the conditions of the output side circuit.

Furthermore, even if the number of output control circuits is increased to three or more stages, simultaneous changes in output can be avoided in the same way, thereby preventing the generation of noise.

〔Effect of the invention〕

As explained above, the output control circuit of the present invention prevents all other outputs from changing when one output is in a transient state, thereby controlling the output control circuit individually by considering the timing of the internal circuit. Since it is not necessary to provide a delay circuit and simultaneous changes in output can be avoided regardless of the conditions of the output side circuit, there is an effect that generation of noise can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a time diagram for explaining the operation of the embodiment shown in FIG.
3 is a block diagram of a second embodiment of the present invention, FIG. 4 is a time diagram for explaining the operation of the embodiment shown in FIG. 3,
FIG. 5 is a block diagram of an example of a conventional output control circuit. 1...Latch circuit, 2...Inverter, 3.4...
・Transfer gate, 5.6...Buffer gate,
7... Exclusive OR circuit, 101.10z... Output control circuit, 11.12... Delay circuit, A, A,, A2
゜B, B,, B2...Input terminal, c, C,, C2, o
. 0,. 02...Output terminal. Ta, 2 bar I fat 7 birds) 4 times

Claims (1)

[Claims] a first transfer gate whose input terminal is connected to a first input terminal; and a first buffer whose input terminal is connected to the output terminal of the first transfer gate and whose output terminal is connected to the first output terminal. a second buffer gate whose input terminal is connected to the first output terminal; and whose input terminal is connected to the output terminal of the second buffer gate and whose output terminal is the output terminal of the first transfer gate. a second transfer gate connected to the first transfer gate; and a second transfer gate connected to the second transfer gate;
a latch circuit comprising a control circuit that controls conduction and non-conduction between the transfer gate and the second transfer gate in an antiphase manner; An output control circuit comprising: an output transient period detection circuit that performs an exclusive OR with a signal and outputs the result from a second output terminal.