JPH0136199B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a positive latch circuit using a Josephson effect element or a four-junction closed-loop Josephson gate.

Josephson logic circuits are normally operated in a latch mode, so each Josephson junction must be reset to a zero voltage state after each logic operation. Due to these characteristics, an AC power supply system is generally used, and a system is adopted in which data is held in a DC drive latch (DC latch) during the time when the polarity of the power supply changes. However, since this method uses a DC latch circuit, there is a drawback that if the logic circuit is a current injection type, the two circuits cannot be directly connected. In order to overcome these drawbacks, a multiphase pulsating current power supply system has been proposed as a circuit driving system suitable for current injection type logic gates.

To explain this multiphase pulsating current power supply system in the case of the simplest two-phase power supply with reference to _FIG . Master launch n ₀ driven by ₀
and a first combinational logic operation circuit _f0 , and in addition to this, a slave latch _{n1 and a second} Combinational logic operation circuit f ₁
will be established. Each of the latch circuits n ₀ and n ₁ is provided with a function of latching the operation results of the previous stage combinational logic operation circuits f ₁ and f ₀ when the corresponding power supplies I ₀ and I ₁ are turned on. In this way, the circuit f ₀ ,
Even if f ₁ is of the current injection type, the required functions can be satisfied.

Considering this principle, a multiphase pulsating current power supply system requires a circuit that positively latches the input signal information.Conversely, if a positive latching circuit that performs a satisfactory function can be provided, the principle will be satisfied. It can be said that it is possible to realize a multiphase pulsating current power supply system that has excellent aspects.

The present invention has been made especially in view of this point, and
The motivation is to provide a positive latch circuit that is necessary and optimal for the above-mentioned multiphase pulsating current power supply system. However, as will be apparent from the description below, the direct purpose of the present invention is to provide a highly reliable positive latch circuit that positively latches input signal information, and its use is as follows. Therefore, it is not limited to the above-mentioned polyphase pulsating current power supply system, but also analog-
Applications to other functional circuits such as digital (A/D) converters are also freely permissible.

Embodiments of the present invention will be described below with reference to FIG. 2 and subsequent figures.

FIG. 2 shows a positive latch circuit 1 as a basic first embodiment of the present invention. In this circuit 1, a current injection type closed Lube Josephson switching gate 2, which may be the same, is used. I use two.

This Josephson switching gate 2, 2 used for the first gate part _G1 and the second gate part _G2 , respectively.
is a well-known and existing gate, and is also called a four-junction closed-loop (4JL) gate.

That is, the basic configuration of this 4JL gate 2 is disclosed in Japanese Patent Application Laid-open No. 56-32830 by the present inventor, and has been improved by adding an input resistor to increase the reliability of input/output separation. Including patent application No. 175113-1975, which was subsequently filed and should be published soon.
It has also been made public and attracting attention through other magazines, conference presentations, etc. As a result, even if the name 4JL gate is used, those skilled in the art can immediately recall its structure and operation, and it is treated as if it were a new academic term.

Therefore, this book also uses the expression 4JL gate. The number "4" is the number of Josephson junction elements related to the basic operation,
The actual number may vary for individual gates.

In the explanation of the operation of the latch circuit 1, each gate G ₁ ,
Since it is also necessary to explain the operation of the _G2 to 4JL gates 2 themselves, we will first describe the 4JL gates themselves with reference to FIG.

A closed loop 3 is constructed using four Josephson junction elements in which a tunnel barrier layer is sandwiched between a pair of upper and lower superconductors, and a pair of circuit current lines 4 and 5 are connected to the closed loop 3. Generally, among this pair of current lines, the connection point P G of the line 4 connected to the hot side with the closed loop 3 is the gate terminal P _G , and the connection point P _E of the line 5 dropped to the ground side is the earth side terminal P _G. Call it _E , and with these terminals P _G and P _E as fields,
The positions of the terminals P _G and P _E are selected so that the number of Josephson junction elements included in each of the right circuit 3R and the left circuit 3L of the closed loop 3 is two.

A pair of Josephson junction elements J ₁ , J ₂ in one branch or branch, in the case shown, the left branch 3L.
An input terminal P _C , generally called a control terminal, is provided between them, and an injection input current I _C is applied to it. in general,
The circuit current Ig to the closed loop 3 is called a gate current, and the current injected to the input terminal P _C is called a control current, and the input terminal is also called a control terminal.

Recently, in addition to this basic configuration, an input resistor R _S is added between the control terminal and the ground or the ground side terminal to ensure input/output separation.

Although it is not directly mentioned in the patent applications already filed, as is already known from subsequent patent applications, conference presentations, publication disclosures, etc. Regarding the critical _{current I 0 of the} device (representative of If you compare branches to each other,
The critical current value of each element in the branch without control terminal P _C , in this case, elements J ₃ and J ₄ , is higher than that of the element in the other branch, in this case, the element in the left branch.
It is larger than that of J ₁ and J ₂ and preferably about 2 to 3 times. If the critical current value of element J ₁ is expressed as I ₀₁ , the above becomes the following equation.

n・I ₀₁ = n・I ₀₂ = I ₀₃ = I ₀₄ (=n・I ₀ ) …(1) n = real number (preferably 2 to 3) This is the current gain A for the operation described below.
This is to obtain =Ig ₀ /I _C and to ensure that a required threshold curve is obtained by different injection sequences of injection currents Ig and I _C.

In general, the operation of the basic gate 2 is often explained in terms of a sequence in which a gate current Ig is passed through the closed loop 3 and then a control current I _C is applied or not.

If this sequence is followed, the threshold curve F of the gate 2 in the Ig-I _C coordinate becomes as shown in Figure 4A. The shaded area surrounded by curve F and each coordinate axis is the zero voltage state area as gate 2, curve F
The upper part is the voltage state or resistance state region.

Assuming that, as the gate current Ig, a current with a current value at point A, which does not exceed the critical current value _IG for the gate, is given to the closed loop 3 as shown by arrow fg, at this point, the gate current Ig is divided into left and right branches. 3L and 3R flow in a shunt manner according to the element critical current difference or inductance difference between both branches, flow out from the common earth side terminal P _E , and both elements J ₁ in the left branch where the critical current value is small, J ₂ is also in a zero voltage state.

Here, when a control current I _C of a magnitude exceeding curve F (point B) is passed in accordance with gate current Ig, point A
crosses the threshold curve F laterally at point _C as shown by the horizontal arrow fT, transitions to point P, and gate 2 is in a voltage state, that is, there is a significant resistance value between both terminals P _E and P _G. It is in a state where it is formed.

This can be explained as follows. When the control current I _C with the value shown at point B is input to the control terminal P _C , this current
I _C is divided into two paths: one goes counterclockwise to the ground terminal P _E via element J ₂ , and the other goes clockwise to the terminal P _E via elements J ₁ , J ₃ , and J ₄ . However, since the gate current Ig has already been applied, even though they are in the same left branch and have the same critical current value, the shunts of both currents I _C and Ig are in opposite directions with respect to element J ₁ , and on the other hand, Since the directions are the same for the element _J2 , only the element _J2 which is now in the same direction can be transitioned to a voltage state by superimposing the two current shunts.

In this way, if element _J2 in the left branch can be opened, the gate current Ig will flow exclusively through the right branch 3R, and the control current also has an impedance path lower than the resistance R _S at this point. It begins to flow through the path to the elements J ₃ and J ₄ and the terminal _PE via the element J ₁ .

Therefore, this time, gate current Ig and control current I _C
The superimposed effect with most of the voltage causes elements J ₃ and J ₄ to switch to a voltage state. At this point, the control current I _C consists of a shunt that flows through the input resistor R _S and a shunt that flows through the last remaining element J ₁ , which is still at zero voltage, to the load resistor R _L held in parallel with the gate. The gate current Ig can also be considered as the sum of the shunts to both the resistors R _S and R _L , but as is already known, the gate current Ig can be considered as the sum of the shunts to the resistors R _S and
When R _L is set to an appropriate value, the gate current shunt becomes dominant among the two current shunts in opposite directions with respect to element J ₁ , and the resistance is increased through this element J ₁ .
This element J ₁ with the corresponding gate current shunt flowing through R _S
can be switched to a voltage state. Incidentally, from simple calculation, this condition is expressed by the following formula.

Ig・R _L /R _S +R _L −I _C・R _S /R _S +R _L ≧I ₀₁ (=I ₀ ) …(2) When element J ₁ switches in this way, the control current I _C as input current is exclusively Flows only through the input resistor R _S ,
On the other hand, almost all of the gate current Ig flows to the load resistor R _L as an output current Ig ₀ . Therefore, input/output separation can be ensured, and the output current level can be stabilized. However, in principle, switching operation can be ensured even without the input resistance R _S.

Furthermore, as mentioned above, if the critical current value of the Josephson junction element is different between the left and right branches, and in this case the value belonging to the right branch is larger, the I _C and Ig axes in Figure 4A are Assuming the same scale, the slope of the portion of the threshold curve F used for operation becomes larger than 45°, that is, a gain can be obtained (A=Ig ₀ /I _C >1).

In Fig. 4A, when the gate current Ig is relatively small, the slope of the threshold curve F becomes flat with point D determined from various parameters as a boundary, but this region is not suitable for the operation to obtain gain. is not used. In any case, as described above, in the sequence of applying the gate current I _G and then adding the control current I _C , the threshold curve portion related to the switching operation is a continuous downward sloping portion.

On the other hand, in the sequence of applying the control current I _C and then applying the gate current Ig, the threshold curve F consists of two characteristic curve parts F ₁ and F ₂ as shown in Figure 4B. Become something.

When the control current I _C is first gradually increased, the magnitude of the gate current I _G that is subsequently applied will fall into a linear downward-sloping region where even a smaller value can cause the gate to transition to the voltage state. F ₁ appears, and the explanation of the mechanism in this part can be referred to in accordance with the illustration in Figure 4A.

Therefore, when the value of the control current I _C exceeds point D', a threshold curve portion _F2 occurs where the gate cannot be switched unless the gate current has a considerably large value I _G ', which is generally called a "dead zone". area a ₂
is formed. This can be explained as follows.

When the control current I _C is increased in the direction indicated by the arrow f _C starting from zero vectorwise in the absence of the gate current I _G , a certain point (this point becomes the point D′ according to various parameters) ), for both elements J ₂ and J ₁ in the left branch where the critical current value is small,
A situation occurs in which not only element J ₂ but also element J ₁ is switched by the clockwise shunt of this control current.

Then, the control current I _C flows exclusively through the input resistance R _S ,
The current does not flow into the gate, and the result is a configuration in which two series switching elements J ₃ and J ₄ with large critical currents are simply interposed between the circuit current lines 4 and 5. That is, at this point, the input/output, control, and gate current systems are already independent systems.

Therefore, in order to switch both the remaining elements J ₃ and J ₄ in the right branch, it is necessary to rely solely on the magnitude of the gate current I _G , since there is no interference or overlap with the control current. , its value is the 4th A
This is larger than in the illustrated sequence.

Conversely, the control current I _C is moved by the arrow f _C that crosses point D′
If we increase it to the value of point B′ as shown in
After that, even if the gate current I _G is applied as shown by the arrow f _V to the same value as point A shown in No. 4A, this arrow f _V only reaches point P' within the dead zone, and the threshold curve Since F is not crossed at any of the portions F ₁ and F ₂ , there is no transition to the voltage state of gate 2 .

Therefore, with Figures 4A and B on the same scale,
If points A, A' and points B, B' are the same value, then points P,
P′ is also in the same position, but when the control current f _T is applied under the bias of the gate current f g , gate 2 transitions to the voltage state, and the gate current f _V under the bias of the control current f _C A sequence-dependent switching operation is obtained in which a zero voltage state is maintained when the voltage is applied.

However, in other circuit applications that utilize sequence-dependent dual threshold curves, the curve portion related to the operation in FIG. 4A can be substituted with the portion _F1 in FIG. 4B, and the operation that crosses point C' in the right direction Therefore, generally, such an operation is often explained only by the curve shown in FIG. 4B.

Incidentally, in order to obtain the curve portion F ₂ shown in FIG. 4B, no matter what the critical current values of the elements J ₃ and J ₄ in the right branch are, that is, even without considering the gain, the elements J 1 and J ₁ in the left branch are It is necessary to be larger than that of J ₂ . This is because if they are the same, both elements J ₃ and J ₄ in the right branch may also transition to the voltage state when element J ₁ is switched by the clockwise branch of control current I _C . However, in general, as mentioned above, considering the gain, the critical currents I ₀₁ and I ₀₂ of the elements J ₁ and J ₂ are set as n=2 to 3 in the equation (1) mentioned above, and the elements J ₃ , Since I ₀₃ and I ₀₄ of J ₄ are selected,
It is not seen as a problem.

Having explained the basic 4JL gate 2 above, returning to the explanation of the circuit 1 of this embodiment shown in the second diagram,
The gate terminal P _G1 of the 4JL gate ₂₁ used as the first gate section G 1 is connected to the input terminal P _C2 of the 4JL gate 22 of the second latching gate section G ₂ in the next stage via the load resistor R _L1 . There is. Note that the lowest digit number or suffix 1, 2 in each code indicates which of the first and second gates G ₁ and G ₂ it belongs to, respectively. Therefore, for example, if Ig ₀₁ is used, this means the output current of the first gate portion G ₁ which corresponds to the output current Ig ₀ of the basic gate 2 shown in the third diagram.

Control terminal of 4JL gate 21 of first gate section _G1
P _C1 is the timing input terminal T of this latch circuit 1;
The gate terminal P _G1 is also used as the signal input terminal S of the latch circuit 1.

On the other hand, in the case of the 4JL gate 22 of the second gate section _G2 , the output load resistor R _L2 works as it is as a resistor for obtaining the output signal current of this latch circuit, and the gate terminal P _G2 is connected to the power input terminal E of this latch circuit. used as.

The operation of this latch circuit will be explained below with reference to the timing chart shown in FIG.

It is assumed that a power supply current I E is periodically applied to the power input terminal _E of this circuit 1, and when this power supply current I _E is applied, a signal current that is significant as logic “1” is applied to the signal input terminal S. Assume that I _S is given.

The threshold curves shown in Figures 4A and 4B are for both gates 2
1 and 22, the values of the signal current I _S and the power supply current I _E are A = A', and the timing current I _T to be described later.
Assuming that the value of is B=B', the signal current I _S is the gate current Ig ₁ of the first gate 21 (G ₁ ), and the power supply current I _S is the gate current Ig of the second gate 22 (G ₂ ). ₂
Therefore, in this state where no control current is applied, both gates follow the threshold curve shown in Figure 4A, and are biased to point A in the zero voltage state as shown by arrow fg. Become.

Here, as shown at time t=1 in FIG.
When the timing current I _T is applied to the terminal T, this current is the control current I _C1 of the first gate, and its magnitude is the value of point B in FIG. 4A as described above, so As shown by the arrow f _T in the threshold curve,
The threshold curve F is crossed at a point C and a point P is reached, and this gate 21 transitions to a voltage state.

When this first gate 21 transitions to a voltage state,
Due to the mechanism described above, the timing current I _T flows exclusively through the first gate input resistor R _S1 ,
The signal current I _S flows exclusively toward the output resistor R _L1 as the output current Ig ₀₁ of the first gate 21 .

This output current Ig ₀₁ then flows into the second gate 22 as a control input current I _C2 of the second gate 22 . Here, if points A and B in each figure in FIG. 4 are selected to have the same value for simplicity, switching will occur with respect to the second gate 22 by the same mechanism as the first gate 21.

That is, since the output current Ig ₀₁ from the previous stage with value B (=A) is added as control current I _C2 to the source current I _E of value A that has been given as gate current Ig ₂ in advance, the gate current I The switching of the gate 22 to the voltage state occurs by the sequence of arrows fg and _fT in FIG. 4A, in which the current is applied and then the control current is applied.

As a result, the power supply current I _E becomes the second gate output current
Ig ₀₂ , and eventually the output current I _0Ut of the latch circuit 1 flows to the load resistor R _L2 , and after that, the signal current I _S as logic "1" falls and becomes "0".
Even so, the first gate 21 returns to the zero voltage state and waits, but the second gate 22 maintains the voltage state,
The output current I _0Ut with logic “1” continues to flow to the outside. As a result, the signal logic "1" is affirmatively latched.

First, the magnitude A when the signal current value is viewed as the gate current _Ig1 to the first gate 21, and the time when the first gate 21 switches and is sent to the second gate 22 as the control current _Ic2 . The value of B was set to be the same as that of B, but within the range where the second gate can be switched and the operation according to FIG. 4B described later can be guaranteed.
For example, the value B does not necessarily have to be equal to the value A as long as it is within the range between point D in FIG. 4A and point I _G ' in FIG. 4B. However, in order to simplify the drawing, A=B will also be assumed below.

Next, when the timing current I _T is applied to the terminal T, the signal input S is logic “0”, that is, the signal current I _S
I will explain if it is not flowing. This is the fifth
This corresponds to the state shown at time t=2 in the figure.

In this case, regarding the first gate 21, the operation according to the second sequence described above, that is, first, the control current is
Since the gate current as a signal current may be added in the future after I _T =I _C1 is added, the threshold curve F becomes as shown in FIG. 4B.

When the timing current I _T flows into the control terminal P _C1 of the first gate 21 through the terminal T, the gate 2
1 is biased toward point B' as shown by arrow f _C in FIG. 4B.

At this time, if the signal current I _S is zero, the gate 21 naturally remains in a zero voltage state, and therefore there is no effect on the second gate 22 that follows the threshold curve F in FIG. 4A, and the power supply current I _E The output is a logic "0" because it remains in the A point bias state due to

Since this is a latch circuit, if the reference point for determining the signal for latch operation is set at the rising edge of the timing current I _T , from that point onwards, the power supply current I _E
As long as this continues, it is useless to change the output depending on the signal state.

Input logic “1” during timing signal input →
Regarding the change of “0”, it has already been mentioned that the latching of logic “1” is guaranteed, but if the change of logic “0”
→This latch circuit 1 is of course designed to ensure latching of logic "0" even in the case of a change of "1".

As mentioned above, after the signal logic "0" is latched at time t=2 in FIG.
Assume that the signal logic becomes "1" as shown at time t=3.

This is a sequence in which the signal current I _S as the gate current Ig ₁ is added when the timing current I _T is applied to the first gate 21 in advance, so the threshold curve F is the fourth B as described above. Please follow the illustrations. This means that, as shown by the arrow f _C , there is a transition from a biased state to point B' to point P' along arrow f _V , and this is a "dead zone" a ₂ It's just a change within.

Therefore, the first gate 21 will still remain in the zero voltage state, and the signal current I _S will flow out to the ground via the first gate right branch 3R.
There will be no effect on the second gate 22. In the end, as shown in the time interval _T1 between times t=4 and 5 in FIG. 5, the output result is the same as when the signal logic continues to be "0" during one frame.

In this manner, the present latch circuit can positively latch input signal information at the rising edge of the timing signal.

Next, from a practical point of view, considering the operating margin regarding current, the dead zone a ₂ in Fig. 4B
It is better that the critical current value I _G ' of the threshold curve F ₂ portion forming the first region portion a ₁ is closer to the maximum critical current value I _G in the curve portion F ₂ forming the first region portion a 1 , that is, larger.

To satisfy this requirement structurally, the circuit configuration shown in FIG. 6 can be considered.

The difference from the first embodiment shown in the second diagram is that in the timing signal current line to the control terminal _PC1 of the 4JL gate 21 of the first gate section _G1 , when the gate current is zero, this gate is An input Josephson junction element Ji with a critical current I _0i smaller than the control current value (this value is I _C0 ) that causes not only element J ₂₁ but also J ₁₁ in the left branch 3L of the closed loop 3 to be in a voltage state is interposed in series. However, the input resistor R _S1 is inserted between the external end of this element Ji and the ground, and other configurations (including physical configuration and line connection configuration) may be the same as in the first embodiment. . Therefore, in FIG. 6, components corresponding to those in the first embodiment are given the same reference numerals, and some explanations will be omitted.

In this way, Josephson junction elements with relatively low critical current values Ii < I _C0 are used in the timing current line.
When Ji is inserted, in particular, the sequence in which the timing current I _T as the control current I _C1 is applied to the 4JL gate 21 and then the signal current I _S as the gate current Ig ₁ is applied, that is, as shown in the threshold curve F shown in Figure 4B. At times t=2 and t= in FIG. 5, parts F ₁ and F ₂ appear at
3, in a rising transient state that reaches a timing current of more than a certain degree, for example a value B', the input Josephson junction element Ji switches on first.

Therefore, from now on, almost all of the timing current I _T flows through the input resistor R _S1 , and the 4JL gate 2
It never flows into 1.

Therefore, when this state is realized, the four junctions J ₁₁ , J ₂₁ , J ₃₁ , and J ₄₁ of the gate 21 all have gate currents.
Since only the possibility of being switched by the signal current I _S as Ig ₁ remains, the possibility is greater than switching only the two elements J ₃₁ and J ₄₁ in the right branch 3R as in the previous embodiment. If the current value is not the same, the voltage state of the gate 21 cannot be changed.

If this is shown as a change in the threshold curve, then the
The portion F ₂ in Figure 4B shifts upward in the Ig axis direction like the virtual line threshold curve F ₂ ′, and the gate current region of the dead zone a ₂ expands, increasing the operating margin.

The present circuit 1 shown in FIG. 6 is also completely similar to the first embodiment with respect to other basic latching operations, so a re-explanation will be omitted.

As described above, according to the present invention, the Josephson positive latch circuit reads out an input signal at the instant of the rising edge of the timing signal, and holds and outputs the read signal without being affected by subsequent changes in the input signal. It is possible to provide a latch circuit that is easy to configure while ensuring reliable and reliable operation, and can be used as an important component of a computer circuit system that uses a multiphase pulsating current power supply system, making it possible to realize the Josephson computer. It can also make a significant contribution.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of an example of the field of use of the positive latch circuit of the present invention, Fig. 2 is a schematic configuration diagram of a basic embodiment of the present invention, and Fig. 3 is a basic diagram of an existing 4JL gate used in the present invention. 4 is a diagram of the threshold characteristic curve of the 4JL gate, FIG. 5 is a time chart-like diagram explaining the operation of the first embodiment, and FIG. 6 is a schematic diagram of the configuration of the second embodiment. be. In the figure, 1 is the positive latch circuit as a whole, 2, 21, 22 are 4JL gates, 3 is a closed loop, S is a signal input terminal, T is a timing input terminal, E is a power supply input terminal, R _L2 is an output load resistance, It is.

Claims (1)

[Claims] 1 includes a Josephson junction element, a gate terminal,
Two current injection type closed loop Josephson switching gates having three terminals, a ground terminal and a control terminal, are used as the first and second gates, and the control terminal of the first gate is used as a timing input terminal, and the above gate terminal is used as a timing input terminal. In addition to serving as a signal input terminal, the gate terminal of the first gate is connected to the control terminal of the second gate, while the gate terminal of the second gate is used as a power input terminal, and the gate terminal of the second gate is connected to the ground. A Josephson positive latch circuit characterized by selectively drawing an output current to a load resistor interposed between side terminals.