JPS6334657B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the configuration of a non-latching logic circuit that can be driven by a DC power source and uses Josephson junctions.

Conventional logic circuits using Josephson junctions have mainly been studied using AC power supply systems. This AC power supply drive system was developed out of a desire to temporarily reduce the power supply voltage to zero, since Josephson junctions are often used as latching gates. However, this had the problem that the circuit would latch even if an erroneous impulse signal was input, and there was a high possibility that erroneous calculation results would be output, making the circuit unreliable in practice. There was also a great risk that the circuit would latch just by switching the power supply. For this purpose, a DC power-driven non-latching
One challenge was using the gates.

Furthermore, as a conventional logic gate using a Josephson junction that can perform the NOT function, the voltage balanced circuit shown in Fig. It was known. However, this method only requires one output (OR or OR if there are two input lines).
There was a drawback that only one of the NOR logics could be obtained. Also, since this method uses in-line gates, if you want to design the output current to be arbitrarily large, the two junctions g ₀₁ and g ₀₂ should be set at 25μ on each side.
It was necessary to design the circuit with a large area of about 100 m, making it difficult to increase the speed of circuit operation. Furthermore, the value of the voltage applied to the two junctions g ₀₁ , g ₀₂ and the resistor R _s connected in series is greater than 1 times the voltage V _g =2Δ/e corresponding to the gap energy of the junctions and 2 There was a drawback that it only worked if the setting was smaller than double.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a logic circuit that can simultaneously obtain operation outputs of OR logic and NOR logic. of the present invention
By using the OR/NOR logic circuit, all logic can be configured based on this, so a highly versatile logic gate for integrated circuits can be provided.

The present invention will be described in detail with reference to Examples below.
Initially, the supply voltage is suitable and the voltage across the two cascaded junction switches and the resistor R _s is V _g .
The operation of the circuit of the present invention shown in FIG. 2 when set to an intermediate value of 2V _g will be described in comparison with the voltage balanced circuit shown in FIG. 1. Fig. 1 Josephson junction switch with two magnetic field coupling input methods
A combination of g ₀₁ and g ₀₂ or a combination of g ₁₁ and g ₁₂ in Figure 2, or a combination of g ₂₁ and g ₂₂ connected in parallel by a superconducting wire and a resistor connected to the DC power line P ₁ The voltage applied to R _s and V _g +α (0<α<
V _g ). The series resistance R _D on the ground line side in FIG. 2 may basically be zero. When this resistance R _D is zero, the second
The configuration shown in the figure is similar to the configuration in which two pairs of voltage balance circuits in FIG. 1 are arranged side by side.

In Figures 1 and 2, the input signal line (indicated by IN in Figure 1 and IN1 in Figure 2)
Let us consider the case where no input current is flowing (input is "0" state) (indicated by IN2 and IN2). At this time,
The connection switch g ₀₁ on the upper side of Figure 1, the connection switch g ₂₁ on the upper right side of Figure 2, the connection switch on the lower left side
Since no magnetic field is applied to g ₁₂ , each junction is in a state where superconducting current can flow. on the other hand,
The connection switch g ₀₂ on the lower side of Fig. 1, the connection switch g ₁₁ on the upper left side of Fig. 2, the connection switch on the lower right side
Since the bias current constantly flows in the vicinity of the junction switches g ₁₁ and g ₂₂ through the resistor R _B , a magnetic field is applied to g 22 _, so that no superconducting current flows. At this time, a voltage V _g is generated across the switches g ₀₂ , g ₁₁ , and g ₂₂ . As a result, the DC current passing through the resistor R _s of the voltage balanced circuit is transferred to the output terminal located at the midpoint between junction switches g ₀₁ and g ₀₂ in Figure 1.
OUTPUT (NOT) or junction switch in Figure 2
Output terminal OUTPUT installed at the midpoint between g ₂₁ and g ₂₂
It can flow out from (NOR) (output “1”). but,
From the output terminal OUTPUT (OR) installed at the midpoint between junction switches g ₁₁ and g ₁₂ in Fig.
Since g ₁₁ exhibits a finite resistance, it cannot flow out (output “0”).

Next, the input current flows through the input signal line IN in Figure 1,
Consider a case where an input current flows through one or both of the input signal lines IN1 and IN2 in FIG. 2 (input is "1" state). At this time, a magnetic field is applied to the junction switches g ₀₁ , g ₁₂ , and g ₂₁ , and a voltage V _g is generated across them. On the other hand, to the junction switches g ₀₂ , g ₁₁ , and g ₂₂ , the magnetic field generated by the input current and the magnetic field due to the bias current applied in the direction that cancels this are simultaneously applied, effectively reducing the total magnetic field. This results in a state in which superconducting current can flow. The pair of junction switches g ₀₁ and g ₀₂ (g ₀₁ + g ₀₂ ), the pair of g ₁₁ and g ₁₂ (g ₁₁ + g ₁₂ ), and the pair of g 21 and g ₁₂ respectively.
Since the voltage applied to the pair with g ₂₂ (g ₂₁ + g ₂₂ ) and the series resistor R _s is set in advance to V _g + α (0 < α < V _g ), in the above state, g ₀₁ and
It is impossible for both g ₀₂ , both g ₁₁ and g ₁₂ , and both g ₂₁ and g ₂₂ to be in a state where they each generate a voltage of V _g (state with resistance). Due to this applied voltage regulation, when an input current flows through the input signal line, g ₀₁ , g ₁₂ , and g ₂₁ exhibit finite resistance. That is, the state is such that a voltage V _g is generated. At the same time, the other junction switches g ₀₂ , g ₁₁ , and g ₂₂ have no choice but to shift to a state where superconducting current flows, that is, no voltage V _g is generated. As a result, the DC current passing through the resistor R _s of the voltage balanced circuit flows only through the junction switch g ₁₁ in Figure 2, and the output current flows through the output terminal.
It flows out to the outside through OUTPUT (OR) (output “1”). However, the output terminal OUTPUT (NOR) installed at the midpoint between g ₂₁ and g ₂₂ in Figure 2, and the
Output terminal installed at the midpoint between g ₀₁ and g ₀₂ in the diagram
From OUTPUT (NOT), the junction switches g ₂₁ and g ₀₁ exhibit finite resistance, so there is no flow (output “0”).

After this, when the current in the input signal line becomes zero again (input "0"), the superconducting current flows from the output terminal of OUTPUT (NOT) in Figure 1 and OUTPUT (NOR) in Figure 2 due to the same operating principle. The state output "1") which is outputted can be realized.

In this way, when the applied voltage is regulated, the circuit in Figure 1 performs the NOT function and the second
It has become clear that the circuit shown in the figure performs NOR and OR functions, and that they can output signals to the outside depending on the presence or absence of input signal current.

The circuit of the present invention shown in FIG. 2 differs from the known voltage-balanced circuit shown in FIG. (2) Instead of using a single Josephson junction (also called an in-line gate) as a junction switch, it is possible to use other magnetic field input type gates, such as quantum interference type gates. (3)Furthermore, four junction switches were connected in a loop to provide the following new effects.

The effect of connecting the four junctions in a loop is that it is no longer necessary to regulate the power supply voltage to V _g +α (0<α<V _g ). In this case, the value of the current flowing through the resistor R _s on the power supply side in Fig. 2 is the maximum superconducting current that can flow through the set of two Josephson junction switches (g ₁₁ + g ₁₂ , g ₂₁ + g ₂₂ ) connected in cascade. current
It is sufficient if it is set smaller than I _n . The operation at this time is as follows. For example, if an input current is flowing from the input signal line and suddenly becomes zero, a magnetic field is suddenly applied to the junction switches _g11 and _g22 , and the superconducting current is cut off. At this moment, at the moment when this current stops flowing, a reverse voltage is instantaneously generated across the junction switches g ₁₁ and g ₂₂ , so it can be considered that the superconducting current has stopped flowing. This reverse voltage is applied to each junction switch g ₁₂
Since the voltage V _{g that has been applied to the junction switches g 12 and g 21 is instantaneously applied to the junction switches g 12 and g 21, it can be canceled by the reverse voltage −V g ( same magnitude and} different sign). As a result, the voltages across junction switches g ₁₂ and g ₂₁ become zero instantaneously and almost simultaneously. Furthermore, at this time, since the magnetic field is no longer applied to the junction switches _g12 and _g21 , the junction switches _g12 and _g21 transition to a state in which superconducting current can flow. In this example, the output current actually flows out of the output terminal OUTPUT (NOR) through the junction switch _g21 . Output terminal
No current flows from the OUTPUT (OR) terminal because the connected junction switch _g11 is in a resistive state. The feature of this circuit is that since the junction switch g ₁₂ is in a state where superconducting current can flow, the signal current that was flowing to the output terminal OUTPUT (OR) until just before is quickly removed to the ground wire through the junction switch g ₁₂ . It is possible to do this.
For this purpose, it is preferable that the series resistance R _D on the ground line side is small, and this value may be zero.

As the Josephson junction switch used in the present invention, it is also possible to use an in-line gate (simple Josephson junction) as shown in FIG. 1, but here we will use the in-line gate shown in FIG. It is more desirable to use such a quantum interference gate. This gate includes a plurality of Josephson junctions in parallel and has a structure (FIG. 3) in which two superconducting loops are provided. The current (I) and voltage (V) characteristics of this gate are similar to those of a single Josephson junction.
It has the shape shown by the thick line in the figure. The state in which superconducting current flows is branch J in the figure, and the state in which superconducting current does not flow is branch G in the figure.

FIG. 5 is a diagram showing another embodiment of the present invention.
The circuit in Fig. 5 differs from the circuit in Fig. 2 described above in that the loop connections connecting the four junction switches g ₁₁ , g ₁₂ , g ₂₁ , and g ₂₂ include resistors R ₁₁ , R ₁₂ , and R _{twenty one} ,
This is the introduction of R ₂₂ . In the figure, the resistor R _D is set to 0, and although this resistor R _D is not shown, it is not essentially different from the circuit shown in FIG. 2. This has the effect of preventing noise magnetic flux that is not a signal from being captured in the loop connection.

As described above, according to the present invention, OR/
It is possible to provide logic gates for φ integrated circuits that can simultaneously output NOR logic outputs, are highly versatile, and can be driven by a DC power supply. The output current can be arbitrarily designed by increasing the allowable current value of the junction switch.
This output can be used as is as an input signal for the next stage logic gate. Furthermore, since the logic circuit of the present invention is of a non-latching type, the circuit is free from errors in calculations and has excellent reliability. For the above reasons, it is clear that the present invention is useful as a basic logic circuit system used in high-speed logic devices (ultra-high-speed computers).

[Brief explanation of the drawing]

Figure 1 is a diagram showing the configuration of a conventionally known voltage balance type circuit, and Figure 2 is a diagram showing the configuration of a conventionally known voltage balance type circuit.
A diagram showing an embodiment of the OR/NOR logic circuit, FIG. 3 is a diagram explaining in detail the configuration of a Josephson junction switch used in the OR/NOR logic circuit of the present invention, and FIG. 4 shows the junction switch of FIG. 3. FIG. 5 is a diagram showing another embodiment of the present invention.

Claims (1)

[Claims] 1. Two types of independent magnetic field coupling input type Josephson junction switches g ₁₁ and g ₁₂ are first connected in series,
A basic circuit consisting of a unit circuit with an output terminal connected to its midpoint, another unit circuit consisting of junction switches g ₂₁ and g ₂₂ connected in parallel via a superconducting wire or a resistor, and this basic circuit. The upper side is connected to the DC power line via a series resistor, and the lower side of this basic circuit is connected to the ground line directly or via a resistor, and a bias magnetic flux is generated that simultaneously interlinks with the junction switches g ₁₁ and g ₂₂ . A bias input loop is provided, and two magnetic field coupling input lines are installed so as to generate magnetic flux that simultaneously links the junction switches g ₁₁ and g ₁₂ and g ₂₁ and _{g 22 .} By combining the input magnetic flux to g ₂₂ and the bias magnetic flux so that their signs are opposite, an OR output is obtained from the midpoint of the junction switches g ₁₁ and g ₁₂ , and a NOR output is obtained from the midpoint of the junction switches g ₂₁ and g ₂₂ . A superconducting DC drive logic circuit characterized by taking out. 2. In claim 1, the value of the voltage applied to each of the unit circuits is set to be greater than 1 time and less than 2 times the voltage V _g =2Δ/e corresponding to the gap energy of the junction. A superconducting DC drive logic circuit characterized by: 3. A superconducting direct current drive logic circuit according to claim 1, characterized in that quantum interference type magnetic field coupling input type gates are used as the junction switches g ₁₁ , g ₁₂ , g ₂₁ , and g ₂₂ . 4. Claim 1 is characterized in that after the magnetic field coupling input lines are coupled to g ₁₁ and g ₁₂ and g ₂₁ and g ₂₂ , respectively, the grounding wires are connected to each other via a terminating resistor. Superconducting DC drive logic circuit.