JPS595491A - Josephson affirmative latch circuit - Google Patents

Abstract

PURPOSE:To realize a reliable latch circuit, by reading an input signal at the moment of rising of a timing signal, and operating as a Josephson affirmative circuit that holds the read signal and outputs without influenced by subsequent change of input signal. CONSTITUTION:It is supposed that after latching of signal logic 0 at a time t1, signal logic becomes 1 at a time t2. This becomes a sequence that when timing current Ir is applied to the first gate 21, a signal Is is added as gate current Is1, and accordingly, the curve F of threshold value becomes as shown in the figure. That is, it becomes a sequence of change from the state of being biassed at a point B shown by the arrow fc to P' along the arrow fv, and this is no more than change in a blind sector a2. The first gate 21 remains in a state of zero voltage, and a signal current Ig flows out to the ground through right branch 4, and exerts no influence on the second gate 22. By this way, input signal information can be latched affirmatively at the time rising of the timing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a positive launch circuit using a Josephson effect element or a four-junction closed-loop Josephson gate.

Since Josephson logic circuits normally operate in a latch mode, each Josephson junction must be reset to a zero voltage state each time a logical operation is performed. Due to these characteristics, an AC power supply system is generally used, and the time during which the polarity of the power supply changes is determined by a DC drive latch (DC latch).
A method of retaining data is adopted. However, in this method, since a DC latch circuit is used, if the logic circuit is a current injection type, there is a drawback that the two circuits cannot be directly connected. In order to overcome these drawbacks, a multiphase pulsating current power supply system has been proposed as a circuit driving system suitable for current injection type logic gates.

In the case of the simplest two-phase power supply, which is the polyphase pulsating current power supply system, the explanation will be given with reference to FIG. 1, which shows a calculation system loop. , 7) Power supply current or clock current■. The master latch rLo and the first combination logic operation circuit f are provided with a master latch rLo driven by and the second combinational logic operation circuit f. And each latch circuit n
o, rL, the corresponding power supply I. , I, the previous stage set fft e logic operation circuit f, , f
, the function to latch the operation result is lost. In this way, the circuit f. Even if +f+ is a current injection type, the required function can be satisfied.

Considering this principle, the multiphase pulsating current power supply system f requires a circuit that positively latches the input signal information.Conversely, if a positive latch circuit that operates with satisfactory functionality can be provided, the principle It can be said that it is possible to realize a multiphase pulsating current power supply system that has excellent aspects.

The present invention has been made especially in view of this point, and is motivated by the provision of a positive latch circuit that is necessary and optimal for the above-mentioned multiphase pulsating current power supply system. However, as will be apparent from the description below, the direct purpose of the present invention is to provide a highly reliable positive latch circuit that positively latches input signal information, and its use is as follows. Therefore, it is not limited to the above-mentioned polyphase pulsating current power supply system, but also analog
Applications to other functional circuits such as digital (A/'D') converters are also freely permissible.

An embodiment of the present invention will be described below with reference to FIG. 2 and subsequent figures.

Although FIG. 2 shows a positive latch circuit as a basic first embodiment of the present invention, in this circuit there are two current injection closed loop Josephson switching gates, which may be the same. I am using it.

This Josephson switching gate is used for the first gate section Gl and the second gate section G2.

λ is a known and existing gate, and is also called a four-junction closed-loop (abbreviated as 4JL) gate.

That is, the basic configuration of this 4JL gate is disclosed in Japanese Patent Application Laid-Open No. 56-32830 written by the present inventor, and has been improved by adding an input resistor to increase the reliability of input/output separation. This includes Japanese Patent Application No. 175113/1987, which was subsequently filed and is expected to be published soon, and has been made publicly known through magazines, conference presentations, etc., and is attracting attention. As a result, even if the name 4JL gate is used, those skilled in the art can immediately recall its structure and operation, and it is treated as if it were a new academic term.

Therefore, in this book as well, the expression 4JL gate will be used. However, the number 4 is the number of Josephson junction elements related to the basic operation, and the actual number may be different for each D gate.

In this latch circuit/f)m description, each gate G1゜G2
Also, the explanation of the operation of the 4JL game itself will be required, so
First, the 4JL Gate itself will be described with reference to Figure 3.

A closed loop 3 is constructed using four Josephson junction elements consisting of a tunnel barrier layer sandwiched between a pair of upper and lower superconductors, and a pair of circuit current lines is connected to this closed loop 3! , 51 connect.

Generally, a connection point P between the closed loop 3 of the line group connected to the hot side of the pair of current lines. gate terminal P.

, the connection point PE of the line S dropped to the ground side is called the ground side terminal PI, and with these terminals Pa and Pg as fields, it is connected to the right circuit 3R and the left circuit 3L of the closed loop 3. The positions of the terminals pc l pE are selected so that the number of Josephson junction elements is two each.

One technique circuit or branch, left branch 3 in the case shown
A pair of Josephson junction elements Jl in L.

An input terminal P0, generally called a control terminal, is provided between J2, and an injection input current rck is applied to it. In general, the circuit current I2 to the closed loop 3 is called a gate current, and the current injected to the input terminal PC is called a control current, and the input terminal is also called a control terminal.

Recently, in addition to this basic configuration, an input resistor R8 is provided between the control terminal and the ground or between the ground side terminal to ensure input/output separation.

Although it is not directly mentioned in the previously-filed patent application mentioned above,
K, Josephson junction devices J (
The critical current of the (Xafix omitted is representative of all elements)■.

Regarding , elements J, belonging to the left branch 3L, ,
J, Comrade and Right Branch,...? R [belonging element J3.
+4 have the same critical current value, but when comparing both branches, each element in the branch without the control terminal Pc, in this case, element J3. The critical current value of +4 is much higher than that of the element in the other branch, element J in the left branch, , +2, preferably 2.
It is said to be about 3 times as much. The critical current Ilf of the element, I
If expressed as O+, the above becomes the following equation.

n' rot = n” I[+2 “”IO3=
IO4<””n・Io)11-・(1) Le=real number (preferably 2 to 3) This corresponds to the current gain A=I in the operation described below.

/Ic, and also to ensure that a required threshold curve is obtained due to the difference in the injection sequence of the injection currents Ip and Ic.

In general, such basic gate operation is often explained in terms of a sequence in which a gate current is applied to the closed loop 3 and then a control current IC is applied or not.

When this sequence is followed, the threshold curve F of the gate λ at the It-■c coordinate becomes as shown in Figure 4A. The shaded area surrounded by force to curve F and each coordinate axis is a zero voltage state area as a gate, and the area above curve F is a voltage state or resistance state area.

Assuming the gate current, the critical current value I for this gate is
For example, if a current with a current value at point A that does not exceed Q is applied to the closed loop 3 as shown by arrow f2, at this point, the gate current is the left and right branches JL, JR, which is the element critical current difference between the two branches. A shunt current flows according to the inductance difference and flows out from the common ground side terminal PE, and the pixel JI + J in the left branch with a small critical current value
2 is also in a zero voltage state.

Here, when a control current re (point B) whose magnitude exceeds the curve Fi in accordance with the gate current applied, point A crosses the threshold curve F & point C in the horizontal direction as shown by the horizontal arrow fT, and the point P, and the gate is in a voltage state, that is, both terminals P
A state is reached in which a significant resistance value is formed between +PG and +PG.

This can be explained as follows. When a control current Ic having a value indicated by point B is input to the control terminal Pc, this current IC takes a counterclockwise path to the ground side terminal PE via the element J2, and a clockwise path to the elements J, , J, , J .

However, since the gate current has already been applied,
Even if they are on the same left branch and have the same critical current value, the elements J,
As for the threshold currents Ic and It, the shunts are in opposite directions, while for element J2, they are in the same direction, so only element J2, which is in the same direction, transitions to a voltage state due to the superposition of the shunts from both sides. I can do it.

In this way, if the element Jz& in the left branch can be opened, the gate current Ip4 will flow exclusively in the right branch 3R, and the control current will also flow through the resistance valve Rs at this point.
The current flows through a path to element J3 + +4 and terminal Pm via element Jak, which has a lower impedance path than Jak.

Therefore, in turn, the elements J, , J, switch to the voltage state due to the superimposed effect of the gate current supply and most of the control current IC. At this point, the control current rc is equal to the input resistance RB
The gate current I, can also be thought of as the sum of the shunts to both resistors Rs and RL, but as is already known, if K and both resistors RB and RL are set to appropriate values, both resistors R and R in opposite directions with respect to element J, In the military branch,
The gate current shunt becomes dominant, and this element J.

This is achieved by causing the element J to switch to the voltage state by the gate current branch flowing through the resistor R8 through the resistor R8.

By the way, this condition can be expressed by the following equation from a simple calculation.

■f*RL/klI10RL-■c・Ra/Rs 10R
L≧rot (=I6) - (2) When the element J1 switches in this way, the control current IC as the input current flows exclusively through the input resistor R8, while the gate current flows almost entirely as the output current I. It flows to the resistor RL.Therefore, it is possible to ensure input/output separation and to stabilize the output current level.However, in principle, the input resistor Rs
Even without this, switching operation can be ensured.

In addition, as mentioned above, the critical current value of the Josephson junction element is different between the left and right branches, and in this case, the one belonging to the right branch is more sharp, as shown in Fig. 4A. , if we use the same scale with the same axis, the slope of the part used for the operation of the threshold A straight curve F will be larger than 45°, that is, it will be possible to obtain a gain (A = I, ./r
c>1).

In addition, in FIG. 4A, when the gate current is relatively small,
The slope of the threshold curve F becomes flat in the 0-point field determined from various parameters, but this region is not used for operations that require gain. In any case, as mentioned above,
In the sequence of adding the gate current I(+ and then adding the control tube current Ic), the threshold curve portion related to the switching operation is a continuous downward-sloping portion.

On the other hand, in the sequence of applying the control current Ic & then applying the gate current, the threshold curve F has two characteristic curve parts F, as shown in Figure 4B.
It consists of F2.

First, the control current IC is gradually increased, and then the gate current ■ is added accordingly. As for the size of F1, a linear descending region F1 with a downward slope to the right appears that can cause the gate to transition to a voltage state even if the value is smaller, and the explanation based on the illustration in FIG. 4A can be used for the mechanism in this part.

Therefore, when the value of fQII control current IC exceeds point D',
Unless the gate current has a considerably large value (G'), a threshold curve portion F2 occurs in which gate switching cannot be detected, and a region α2 generally called a dead zone L is formed. This can be explained as follows.

Gate electric IAt I. , /) Is it vectorially zero in the state where there is no? Control current Ic is applied in the direction indicated by arrow fc, which is the starting point.
As the value increases, beyond a point (this point becomes point D' depending on various parameters), the criticality>IE The pixel J2. in the left branch with a small a value. At J, a state occurs in which not only element J2 but also element J switches outside the clockwise branch of this control current.

Then, the control current IC exclusively flows through the input resistance Rsk and does not flow into the gate, and eventually the circuit current line y,
Between J3 and S, two series switching elements with large critical currents are simply connected. This results in a configuration in which J4 intervenes. That is, at this point, the input/output, control, and gate current systems are already independent systems.

Therefore, after that, pixel J3 in the remaining right branch.
In order to switch J
Since c must depend only on the magnitude and there is no interference or overlap with the control current, its value will be greater than in the case of the sequence shown in Figure 4A.

Conversely, if the control current IC is increased to just above point B' as shown by the arrow fc that crosses point D', then the gate current Io will be the same as aA in Figure 4A, 7). Even if the voltage is applied to the value as shown by the arrow fv, this arrow f
v,' only reaches point P' within the dead zone,
Since the threshold curve F never crosses either part eF or 1F2, the gate voltage never changes to a voltage state.

Therefore, if Figures 4A and B are on the same scale, points A and A'
, a B , B'& muttering the same,! = Sult, point P.

P' is also positionally the same, but gu)'Kbttfp
') When one control current is applied under the bias, the gate voltage transitions to a positive voltage state, and it! When a gate current fv is applied under a bias voltage Kr, fc/), a switching operation is obtained in which the voltage state is changed.

However, the use of both sequence-dependent and +threshold curves C
Even in the circuit application of the dragon, the curved part related to the @ work in Fig. 48 can be substituted with the part F1 in Fig. 4B, and can be explained as an action that crosses the point C' in the right direction, so in general, such an action is It is often explained only by the curve shown in Figure 4B.

Incidentally, in order to obtain the curve portion F2 shown in Figure 4B, the elements in the right branch, +31 J, , 7) No matter how much the critical current value is, that is, even without considering the gain, the elements in the left branch, J, , It is necessary that J is larger than that of J. ■The control current is the same. This is because, along with the switching of element J due to the clockwise shunt of , the right branch middle pixel elements J, +4 may also transition to the voltage state. However, in general, as mentioned above, considering the gain, the critical current I01 + of the element J, , J,
For I(+2, element J3. +4 is selected as ros l IO4 with L = 2 to 3 in equation (1) described above, so this is not viewed as a problem.

Now that the basic 4JL gate has been explained, returning to the explanation of the present embodiment circuit shown in the second figure, 7), the gate terminal P of the 4JL gate 2/ used as the first gate part G1.
G is the load resistor RL, & is connected to the input terminal Pc of the 4JL gate Yuco of the second latching gate section G2 in the next stage,
is connected to. In addition, the lowest digit number or suffix 1, 2 of each code is.

It indicates which of the first and second gates G, , G, belong to, respectively. Therefore, for example, ■. 1, this means the output current of the first gate portion G1 corresponding to the output currents I and o of the third basic gate shown in the figure.

Control terminal Pcl of 4JL gate 21 of first gate section G
The timing input terminal T and gate terminal pc of the present latch circuit are also used as the signal input terminal S of the present latch circuit.

On the other hand, in the 4JL gate 12 of the second gate section G2, the output load resistor RL acts as it is as a resistor that can obtain the output signal current of the latch circuit, and the gate terminal PG2 serves as the power input terminal E of the latch circuit. used.

The operation of this latch circuit will be described below with reference to the timing chart shown in FIG.

The power supply input terminal E of this circuit / periodically receives a power supply current I8.
It is assumed that a significant signal current Is is applied to the signal input terminal S as a logic SS I If when this power supply current II is applied.

The threshold curves shown in figures 4A and 4B are for both gates, 2/.

2, signal current I[l and power supply current II
Assuming that the value of is A = A' and the value of timing current It, which will be described later, is B = B', the signal current Is is the first gate)
J/ (Gl> gate current ■, l is off, power supply current 1. is second gate, 2.2 (G2) gate' current I
7. Therefore, in this state where no control current is applied, both gates follow the threshold curve shown in Figure 4A, and are in a zero voltage state and biased to point A as shown by arrow f. Become.

Here, as shown at time t=1 in FIG. 5, when the timing current A is applied to the terminal T, this current is the control current IC4 of the first gate, and its magnitude is as described above. Since this is the value of point B in Figure 48, as shown by the arrow f in the threshold curve, it crosses the threshold curve at point FQC and reaches point P, and this gate 2/ is in the voltage state. Transition.

When this first gate 2/ transitions to the voltage state, the timing current ■T will exclusively flow through the first gate input resistance R[l, due to the mechanism described above, and the signal current Is will flow through the first gate 2/. As the output current is 1°I, the current flows exclusively to the output resistor RL.

This output current is , now flows into the second gate λU as the control input current ■c of the second gate 2.2.

Here, if we choose the same value for point A and point B in each Figure 4 for simplicity, switching by the same mechanism as the first gate 2/2 will also occur for this gate 2.2. get up.

That is, in advance, the gate current I, and the power supply current IN to the value
is given as the control current 1c1 and the value B (-
A) Output current from the previous stage. Since 1 is added,
The fourth step is to apply the control current after the gate current is applied.
Arrow f1 in Figure 8. The jitance of fT causes the gate 22 to switch to the voltage state.

As a result, the power supply current Il+ becomes the second gate output current.

2, and finally the output current of this latch circuit.

■ t flows through the load resistor RL, and after that, even if the signal current ■8 as logic -1 falls and becomes 'ko1, the first gate 21 returns to the zero voltage state and waits, but the second gate 21 returns to the zero voltage state and waits. Gate Q2 maintains voltage state and outputs 1 current as logic 11〃■. Continue to flow ut to the outside. In the end, signal logic (S
There will be 11 positive latches.

Similarly, first, the signal 'current 1' is directly connected to the first gate U/.
Totli style ■, the size A when viewed as l, and the first gate 2/ is switched and controlled to the second gate, 22 #
The value is the same as the value B when it is sent as wL style Ic2, but within the range that can guarantee the second gate switching and operation according to Figure 4B described later, for example, aD in Figure 48. Point I in Figure 4B. The value B does not necessarily have to be equal to the value A as long as it is within the range between ' and DJ'). However, to simplify the drawing, A=B will be used below.

Next, when the timing current IT is applied to the terminal T,
The case where the signal input S is the logic SSOl, that is, the signal current 8 does not exceed M will be explained. This corresponds to the state shown at time t=2 in FIG.

In this case, regarding the first gate controller, the operation according to the second sequence described above, that is, first, the control current IT -■c,
Since the gate current as a signal current may be added in the future after the gate current is added, the threshold curve F becomes as shown in FIG. 4B.

If the timing ring is ``, IT connects the first gate 2 via terminal T.
When the current flows into the control terminal PC, of /, the gate 2/ becomes biased to point B' as indicated by arrow fc in FIG. 4B.

At this time, if the signal current Ig is zero, it is naturally a game) 2/
remains in the zero voltage state, and therefore there is no effect on the second gate 22 which follows the threshold [straight curve F] in FIG. /7.

Since this is a latch circuit, if the timing is determined to be the rising point of the current IT, which is the reference point for determining the signal of the latch operation, as long as the power supply current IE continues after that point, there is no possibility that the output will change depending on the signal state. I don't speak.

Input logic SS 1 //→-1 during timing signal input
It has already been mentioned that the latching of logic N1 is guaranteed for a change in 0I, but also for a change in logic (t
It is designed to ensure latching of 7.

As mentioned above, after the signal logic NOt' is latched at time t-2 in FIG. 5, it is assumed that the signal logic becomes lit 1 /1 as shown at time t=3. .

This is a sequence in which the signal ``current 6'' as the gate current is added when the timing signal T is added to the first gate 2/ in advance, so the threshold curve F is As already mentioned, it follows the illustration in Figure 4B. This means that, as shown by the arrow fc, point B
′ along the arrow fvK from the point P
', and this is only a change within the "dead zone" α2.

Therefore, the first gate will still remain in the zero voltage state, and the signal type iIs will be the first gate right branch, ? Since it flows out to ground via RQ, there will be no effect on the second gate unit. In the end, as shown in the time interval T1 between time t=4 and time t=5 in FIG. 5, the output result is the same as in the case where the signal logic continues to be XXO during the 5-frame V-frame.

In this way, this latch circuit can positively latch the input signal information at the rising edge of the timing signal.

Next, from a practical point of view, considering the operating margin regarding current, a dead zone α2 is formed in Fig. 4B.
Critical current value of 8111M curve F2 part. ' should be closer to the maximum critical current fit Ia in the first region portion a, tX forming curve portion F2, that is, larger.

If this requirement is to be achieved structurally, the circuit structure shown in FIG. 6 can be considered.

The difference from the first embodiment shown in the second diagram is the control terminal Pc of the 4JL gate 2/ of the first gate portion Gl.

When the gate current is zero, not only the element J21 but also Jll in the left brachio notch 3L of the closed loop 3 of this gate are in the voltage state. ) There is also a small critical current I. An input Josephson junction element Jt of L is interposed in series, and the input resistance gB is inserted between the external end of this element Jt and the ground, ) may be the same as in the first embodiment.

Therefore, in FIG. 6, components corresponding to those in the first embodiment are given the same reference numerals, and some explanations will be omitted.

Thus, at timing ', a Josephson junction element J with a relatively low critical current value 1i < Tco is generated in the flow path.
In particular, when inserting i, the control current I in the 4JL gate 2/
A sequence in which a timing current IT as C, is applied and then a signal current I8 as a gate current -, is applied, i.e., a portion F, , F as shown in the threshold curve F shown in Figure 4B.
2 appears at time t=2 in FIG. In the relationship at t=3, the input Josephson junction element J switches first in a rising transient that reaches a timing current of more than 1, eg, 1 increments B'.

Therefore, from now on, the timing current IT will almost always flow through the input resistance Rs,k, and will not flow into the 4JL gate 2/.

Therefore, when this state is realized, there remains only a possibility that the four junctions Jll + J21 + J31 + J41 are switched only by the signal current circuit 8 as gate current), so the previous implementation As in the example, two elements JPI h 54 in the right branch 3R
Unless the current value is larger than that of switching only 1, it is impossible to cause the gate to transition to the voltage state of 1/.

If this is shown as a change in the threshold curve, the portion F2 in Fig. 4B will eventually shift upward in the second axis direction like the virtual line threshold curves F and l, and the gate current region in the dead zone α2 will expand. As a result, the operating margin increases.

This circuit l shown in Figure 6 can also be used for other basic latching operations! , (at tI/-1, Xπ is exactly the same as in the first embodiment, so we refrain from repeating the process.

As described above, according to the present invention, the Josephson signal is read out at the instant of the rising edge of an input timing signal, and is then held at the read signal without being affected by changes in the human input signal and output. Joseph Non. It will also greatly contribute to the realization of computers.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of an example of the field of application of the constant latch circuit according to the present invention, FIG. 2 is a schematic diagram of a basic embodiment of the present invention, and FIG.
Figure 4 is a basic configuration diagram of the existing 4JL gate used in the present invention, Figure 4 is a threshold characteristic curve diagram of the 4JL gate, Figure 5 is a time chart explanatory diagram explaining the operation of the first embodiment, FIG. 6 is a schematic configuration diagram of the second embodiment. In the figure, l is the main D-temperature latch circuit as a whole, and yu. 2/, λ is a 4JL gate, 3 is a closed loop, St1 signal input terminal, T is a timing input terminal, E is an ms input terminal, %R, , is an output load resistance.

Claims (1)

[Claims] A Josephson junction element including a gate terminal. Two current injection type closed loop Joseph non-switching gates with three terminals, a ground terminal and a control terminal, are used as the first and second gates, the control terminal of the first gate is used as a timing input terminal, and the above gate terminal is used as a signal input terminal. The gate terminal of the second gate is connected to the control terminal of the second gate, and the gate terminal of the second gate is used as a power input terminal, and the gate terminal of the second gate and the ground side terminal are connected to the control terminal of the second gate. A Josephson positive latch circuit is characterized by selectively tapping the output current into a load resistor interposed therebetween.