JP2884886B2 - Reset circuit in superconducting memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting memory circuit, and more particularly to a reset circuit for a superconducting memory circuit.

[0002]

2. Description of the Related Art In order to shorten the operation time of a superconducting memory circuit, it is important to shorten the cycle time including the reset time of the drive current as well as the access time. There are a DC method and an AC method as a drive current supply method for the storage circuit. The DC drive system is excellent in low power consumption. However, a reset gate circuit is required to reset the drive current for driving the storage cell, and a sufficient time margin is required when applying the input signal, which is not suitable for high-speed drive. For this reason, recently reported superconducting memory circuits are often of the AC drive type. FIG. 10 shows an example.

FIG. 10 shows a basic type of AC drive type, 101 is a driver gate circuit, 102 is an input signal line, 103 is a memory cell array, 104 is a load resistor,
Reference numeral 5 denotes a bias current line. While the bias current is being applied to the bias current line 105, the input signal line 102
When the input current is applied to the driver gate circuit 101, the driver gate circuit 101 switches to the voltage state, and drives the operating current to the storage cell array 103 and the load resistor 104. Subsequently, when the bias current falls, the driver gate circuit 101 is reset to the superconducting state, and the operating current driven by the storage cell array 103 is L / L determined by the resistance value R of the load resistor 104 and the inductance L of the storage cell array loop. It falls at the time constant of R, and the operation of the storage circuit is completed.

The driver gate circuit 101 has a SQUID
Various types such as a D-type and a resistance-coupling type have been reported, and a special type of driver gate circuit is used in a polarity switching type driving circuit, but the basic operation is the same as that shown in the above example. is there.

[0005]

As shown in the prior art, the superconducting memory circuit requires a means for resetting the driven operating current. In the conventional example, since the AC drive is used, the operating current is automatically reset after the bias current has fallen by inserting a load resistor into the memory cell array loop. However, the inductance of the memory cell array loop is usually as large as several nH, and the time constant L / R is as large as several hundred psec. Therefore, when a high-speed operation such as a clock of 1 GHz is performed, the reset time of the memory circuit is greatly restricted. In the case of DC drive, as described above, the reset gate circuit is inserted into the memory cell array loop, and the reset gate circuit is switched to reset the operating current. At this time, since the reset gate circuit has a high resistance value, the operating current can fall in several tens of psec. However, it is difficult to increase the speed because of the timing of applying the input signal. As can be easily inferred, the reset time itself can be reduced by inserting a reset gate circuit in series with the load resistor even in the case of AC driving, but the timing of the input signal becomes a problem as described above.

An object of the present invention is to provide a reset circuit in a superconducting memory circuit which solves such a problem.

[0007]

According to a first aspect of the present invention, a reset circuit in a superconducting memory circuit comprises a superconducting memory cell array comprising a driving voltage generating section including a driver gate circuit and a reset gate circuit, and a superconducting memory cell array section. In the loop, a gate circuit having an asymmetrical threshold characteristic in the positive and negative directions of the input current is used as the reset gate circuit, and a DC current line is magnetically coupled to the gate circuit.

A reset circuit in a superconducting memory circuit according to a second invention is a superconducting memory cell array loop comprising a driving voltage generating section including a driver gate circuit and a superconducting memory cell array section. A gate circuit having a threshold characteristic that is asymmetric with respect to the positive and negative directions, and a DC current line is magnetically coupled to the gate circuit.

A reset circuit in a superconducting memory circuit according to a third aspect of the present invention is the superconducting memory cell array loop comprising a driving voltage generating section including a driver gate circuit and a reset gate circuit and a superconducting memory cell array section. A magnetic coupling gate circuit magnetically coupled to a superconducting loop composed of a single Josephson junction and a superconducting wiring is used as a circuit, and a part of a DC current line and a part of a bias line of the driver gate circuit are connected to the superconducting loop. It is characterized by being magnetically coupled.

A reset circuit in a superconducting memory circuit according to a fourth aspect of the present invention is a reset circuit in a superconducting memory cell array loop constituted by a driving voltage generating section including a driver gate circuit and a superconducting memory cell array section, wherein Using a magnetic coupling gate circuit magnetically coupled to a superconducting loop consisting of Josephson junctions and superconducting wiring,
A direct current line and a part of a bias line of the driver gate circuit are magnetically coupled to the superconducting loop.

According to a fifth aspect of the present invention, there is provided a superconducting memory cell circuit comprising: a driving gate generating circuit including a driver gate circuit and a reset gate circuit; and a superconducting memory cell array section. As a circuit, a coupling gate circuit in which a DC current line and a part of a bias line of the driver gate circuit are magnetically coupled is used.

A reset circuit in a superconducting memory circuit according to a sixth aspect of the present invention is a superconducting memory cell array loop comprising a driving voltage generating section including a driver gate circuit and a superconducting memory cell array section. A coupling gate circuit in which a line and a part of a bias line of the driver gate circuit are magnetically coupled is used.

[0013]

FIG. 11 shows the IV characteristics of the driver gate circuit. When the driver gate circuit switches at point A, it shifts the operating point to point B along the load line. When the bias current further falls, the operating point returns to the origin as the bias current falls. However, if the reset time of the operating current flowing in the storage cell array loop is longer than the falling time of the bias current as described in the conventional example, the operating point is momentarily reversely biased through the origin, The operating point is moved to point C, and then returns to the origin. C
The moving time from the point to the origin is equal to the reset time of the operating current flowing in the storage cell array loop. According to the present invention, the reset gate circuit is switched using the current flowing in the reverse direction to shorten the reset time of the operating current.

[0014]

(Embodiment 1) FIGS. 1 and 2 are diagrams for explaining an embodiment of the first invention. In FIG. 1, 1 is a driver gate circuit, 2 is an input signal line, and 3 is a DC current. Reference numeral 4 denotes a reset gate circuit, 5 denotes a memory cell array, 6 denotes a load resistor, and 7 denotes a bias current line. FIG. 2 shows threshold characteristics of the reset gate circuit 4. In the drawing, Ib denotes a bias current, Ic denotes an input current, and O, A, and B denote operating points. During the operation of the reset circuit, the origin of the operation of the reset gate circuit 4 is shown in FIG.
O point.

When an input current is applied to the input signal line 2 while a bias current is being applied to the bias current line 7, the driver gate circuit 1 switches to a voltage state, and the operating current is applied to the storage cell array 5 and the load resistor 6. Drive.
Subsequently, when the bias current falls, the driver gate circuit 1 is reset to the superconducting state, and the operating current driven by the storage cell array 5 is determined by the resistance R of the load resistor 6 and the inductance L of the storage cell array loop.
Attempts to fall with the time constant of R. Since the time constant L / R is usually longer than the fall time of the bias current,
A reverse current flows through the driver gate circuit 1 and the reset gate circuit 4.

Since the reset gate circuit 4 has an asymmetric threshold voltage characteristic as shown in FIG. 2 and a DC current is applied, the operating point is shifted to the point B when the bias current is applied, and The conduction state is maintained, but when the bias current falls, that is, when a reverse current flows, the operating point is shifted to the point A and the state transits to the high resistance state (resistance value R '). Therefore, the time constant of the fall of the operating current of the memory cell array loop is changed from L / R to L / (R + R '), and the fall time can be greatly reduced.
When the operating current completely falls, the operating point of the reset gate circuit 4 returns to the point O, and the reset gate circuit 4 returns to the superconducting state.

(Embodiment 2) FIG. 3 is a diagram for explaining an embodiment of the second invention. In FIG. 3, reference numeral 31 denotes a driver gate circuit, 32 denotes an input signal line, 33 denotes a DC current line, and 34
Indicates a memory cell array, 35 indicates a load resistance, and 37 indicates a bias current line. Further, a gate circuit having a threshold characteristic shown in FIG. 2 is used as the driver gate circuit 31 in the present embodiment. During the operation of the reset circuit, a DC current line 33 magnetically coupled with a DC current to the driver gate circuit 31
, The origin of the operation of the driver gate circuit 31 is the point O in FIG.

When an input current is applied to the input signal line 32 while a bias current is being applied to the bias current line 37, the driver gate circuit 31 switches to a voltage state, and the operating current is applied to the storage cell array 34 and the load resistor 35. Drive. When the bias current subsequently falls, the driver gate circuit 31 is reset to the superconducting state, and the operating current driven by the storage cell array 34 is determined by the resistance R of the load resistor 35 and the inductance L of the storage cell array loop. Attempts to fall with the time constant of R. Since the time constant of L / R is usually longer than the fall time of the bias current, a reverse current flows through the driver gate circuit 31.

The driver gate circuit 31 has an asymmetrical threshold voltage characteristic as shown in FIG. 2 and has a direct current applied thereto. Therefore, the operating point is shifted to the point B when only the bias current is applied. The superconducting state is maintained, but when the bias current falls, that is, when a reverse current flows, the operating point is shifted to the point A and the state transits to the high resistance state (resistance value R '). Therefore, the time constant of the fall of the operating current of the memory cell array loop is changed from L / R to L / (R + R '), and the fall time can be greatly reduced. When the operating current completely falls, the operating point of driver gate circuit 31 returns to point O, and driver gate circuit 31 returns to the superconductive state.

(Embodiment 3) FIGS. 4 and 5 are views for explaining an embodiment of the third invention. In FIG. 4, reference numeral 41 denotes a driver gate circuit, 42 denotes an input signal line, and 43 denotes a DC current line. , 44 indicate a reset gate circuit, 45 indicates a memory cell array, 46 indicates a load resistance, and 47 indicates a bias current line. FIG. 5 shows the relationship between the applied current I of a superconducting loop including a single Josephson junction magnetically coupled to the reset gate circuit 44 and the phase θ of the Josephson junction.
In the figure, O, A, and B indicate operating points, respectively. During the operation of the reset circuit, a direct current is applied to the direct current line 43 magnetically coupled to the superconducting loop, so that the origin of the operation of the superconducting loop is point O in FIG.

When an input current is applied to the input signal line 42 while a bias current is being applied to the bias current line 47, the driver gate circuit 41 switches to a voltage state, and the operating current is applied to the storage cell array 45 and the load resistor 46. Drive. Subsequently, when the bias current falls, the driver gate circuit 41 is reset to the superconducting state, and the operating current driven by the storage cell array 45 is determined by the resistance value R of the load resistor 46 and the inductance L of the storage cell array loop. Attempts to fall with a time constant of / R. Since the time constant of L / R is usually longer than the fall time of the bias current, a current flows in the driver gate circuit and the reset gate circuit in the opposite direction.

Since a part of the bias current line 47 is magnetically coupled to the superconducting loop together with the direct current, the operating point of the superconducting loop moves as follows. At the time of the rise of the bias current, a direct current is applied so as to act in a direction opposite to the bias current. Therefore, the operating point of the superconducting loop is shifted to the point B, and the reset gate circuit is magnetically coupled to the superconducting loop. 44 maintains a superconducting state. On the other hand, when the bias current falls, that is, when a current flows in the opposite direction to the rising current, the operating point of the superconducting loop is A
At the point, the reset gate circuit 44 transitions to the high resistance state (resistance value R ') in response to the magnetic flux entering the reset gate circuit 44 magnetically coupled to the superconducting loop. Therefore, the time constant of the fall of the operating current of the memory cell array loop is changed from L / R to L / (R + R '), and the fall time can be greatly reduced.
When the operating current completely falls, reset gate circuit 44 returns to the superconductive state.

(Embodiment 4) FIG. 6 is a view for explaining an embodiment of the fourth invention. In FIG. 6, reference numeral 61 denotes a driver gate circuit, 62 denotes an input signal line, 63 denotes a direct current line, 64
Indicates a memory cell array, 65 indicates a load resistance, and 66 indicates a bias current line. FIG. 5 also shows the relationship between the applied current I of the superconducting loop including a single Josephson junction magnetically coupled to the driver gate circuit 61 and the phase θ of the Josephson junction. During the operation of the reset circuit, a direct current is applied to the direct current line 63 magnetically coupled to the superconducting loop, so that the origin of the operation of the superconducting loop is point O in FIG.

When an input current is applied to the input signal line 62 while a bias current is being applied to the bias current line 66, the driver gate circuit 61 switches to a voltage state, and the operating current is applied to the storage cell array 64 and the load resistor 65. Drive. Subsequently, when the bias current falls, the driver gate circuit 61 is reset to the superconducting state, and the operating current driven by the storage cell array 64 is determined by the resistance value R of the load resistor 65 and the inductance L of the storage cell array loop. Attempts to fall with a time constant of / R. Since the time constant of L / R is usually longer than the fall time of the bias current, a reverse current flows through the driver gate circuit.

Since a part of the bias current line 66 is magnetically coupled with the DC current to the superconducting loop, the operating point of the superconducting loop moves as follows. At the time of the rise of the bias current, a direct current is applied so as to act in a direction opposite to the bias current, so the operating point of the superconducting loop is shifted to the point B, and the driver gate circuit is magnetically coupled with the superconducting loop. 61 keeps the superconducting state. On the other hand, when the bias current falls, that is, when a current flows in the opposite direction to the rising current, the operating point of the superconducting loop shifts to the point A, and the magnetic flux is applied to the driver gate circuit 61 magnetically coupled to the superconducting loop. , The driver gate circuit 61 transitions to the high resistance state (resistance value R ′). Therefore, the time constant of the fall of the operating current of the memory cell array loop is changed from L / R to L / (R + R '), and the fall time can be greatly reduced.
When the operating current completely falls, driver gate circuit 61 returns to the superconductive state.

(Embodiment 5) FIGS. 7 and 8 are views for explaining an embodiment of the fifth invention. In FIG. 7, reference numeral 71 denotes a driver gate circuit, 72 denotes an input signal line, and 73 denotes a DC current line. , 74 are reset gate circuits, 75 is a memory cell array, 76 is a load resistor, and 77 is a bias current line. FIG. 8 shows threshold characteristics of the reset gate circuit 74. In the drawing, Ib is a bias current, Ic is an input current,
O, A, and B indicate operating points, respectively. During the operation of the reset circuit, a direct current is applied to the direct current line 73 magnetically coupled to the reset gate circuit 74, so that the origin of the operation of the reset gate circuit 74 is point O in FIG.

When an input current is applied to the input signal line 72 while a bias current is being applied to the bias current line 77, the driver gate circuit 71 switches to a voltage state, and the operating current is applied to the storage cell array 75 and the load resistor 76. Drive. When the bias current subsequently falls, the driver gate circuit 71 is reset to the superconducting state, and the operating current driven by the storage cell array 75 is determined by the resistance R of the load resistor 76 and the inductance L of the storage cell array loop. Attempts to fall with the time constant of R. Since the time constant of L / R is usually longer than the fall time of the bias current, a reverse current flows through the driver gate circuit 71 and the reset gate circuit 74.

The reset gate circuit 74 has a threshold characteristic as shown in FIG. 8, is applied with a direct current, and a bias current is applied because a part of the bias current line 77 is magnetically coupled. In this state, the input current is applied simultaneously with the bias current, and the operating point is shifted to the point B. As shown in the figure, in this state, the reset gate circuit 74 maintains the superconducting state, but when the bias current falls, that is, when a reverse current flows, the operating point shifts to the point A, and the high resistance state (resistance value) R ′). Therefore, the time constant of the fall of the operating current of the memory cell array loop is changed from L / R to L / (R + R '), and the fall time can be greatly reduced. When the operating current completely falls, the reset gate circuit 4
Returns to the point O, and the reset gate circuit 74 returns to the superconducting state.

(Embodiment 6) FIG. 9 is a view for explaining an embodiment of the sixth invention. In FIG. 9, reference numeral 91 denotes a driver gate circuit, 92 denotes an input signal line, 93 denotes a DC current line, and 94 denotes a driver.
Represents a memory cell array, 95 represents a load resistance, and 97 represents a bias current line. FIG. 8 shows the threshold characteristics of the driver gate circuit 91. During the operation of the reset circuit, a direct current is applied to a direct current line 92 magnetically coupled to the driver gate circuit 91, so that the driver gate circuit 9
The origin of the operation 1 is the point O in FIG.

When an input current is applied to the input signal line 92 while the bias current is being applied to the bias current line 97, the driver gate circuit 91 switches to a voltage state, and the operating current is applied to the storage cell array 94 and the load resistor 95. Drive. When the bias current subsequently falls, the driver gate circuit 91 resets to the superconducting state, and the operating current driven by the storage cell array 94 is determined by the resistance value R of the load resistor 95 and the inductance L of the storage cell array loop. Attempts to fall with a time constant of / R. Since the time constant of L / R is usually longer than the fall time of the bias current, a reverse current flows through the driver gate circuit 91.

The driver gate circuit has a threshold characteristic as shown in FIG. 8, is applied with a direct current, and has only a bias current applied since a part of the bias current line 97 is magnetically coupled. In this state, the input current is applied simultaneously with the bias current, and the operating point is shifted to the point B. As shown in FIG.
1 keeps the superconducting state, but when the bias current falls, that is, when a reverse current flows, the operating point is shifted to the point A and transits to the high resistance state (resistance value R '). Therefore, the time constant of the fall of the operating current of the memory cell array loop is changed from L / R to L / (R + R '), and the fall time can be greatly reduced. When the operating current completely falls, the driver gate circuit 91
Returns to the point O, and the driver gate circuit 91 returns to the superconducting state.

[0032]

An effect common to the first to sixth inventions is that the reset time is greatly reduced. That is, the transition of the reset gate circuit or the driver gate circuit to the high resistance state at the time of the fall of the bias current changes the time constant of the fall of the operation current of the memory cell array loop from L / R to L / (R + R ′). Let
The fall time can be greatly reduced. Further, the switch of the reset gate circuit or the driver gate circuit uses the reverse current flowing in the bias current line when the bias current falls, and does not require a timing signal or the like. Therefore, a reduction in the cycle time of the storage circuit can be expected.

Further, in the second, fourth and sixth aspects of the invention, the function of the reset gate circuit is added to the driver gate circuit, so that the circuit can be downsized.

In the third and fourth inventions, since the direct current is not directly coupled to the driver gate circuit or the reset gate circuit, the operation margin of each gate circuit can be expanded.

In the fifth and sixth aspects of the present invention, a gate circuit having symmetrical threshold characteristics can be used for the driver gate circuit or the reset gate circuit, so that the operation margin can be expanded.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the first invention.

FIG. 2 is a diagram illustrating threshold characteristics of a reset gate circuit.

FIG. 3 is a circuit diagram of an embodiment of the second invention.

FIG. 4 is a circuit diagram of an embodiment of the third invention.

FIG. 5 is a diagram showing a relationship between a current applied to a superconducting loop and a phase of a Josephson junction used in an embodiment of the third and fourth inventions.

FIG. 6 is a circuit diagram of an embodiment of the fourth invention.

FIG. 7 is a circuit diagram of an embodiment of the fifth invention.

FIG. 8 is a diagram illustrating threshold characteristics of a reset gate circuit or a driver gate circuit.

FIG. 9 is a circuit diagram of an embodiment of the sixth invention.

FIG. 10 is a diagram for explaining a conventional example.

FIG. 11 is a diagram showing an IV characteristic of a driver gate circuit for explaining the operation of the present invention.

[Explanation of symbols]

1, 31, 41, 61, 71, 91 Driver gate circuit 2, 32, 42, 62, 72, 92 Input signal line 3, 33, 43, 63, 73, 93 DC current line 4, 44, 74 Reset gate circuit 5, 34, 45, 64, 75, 94 Storage cell array 6, 35, 46, 65, 76, 95 Load resistance 7, 37, 47, 66, 77, 97 Bias current line

Continuation of the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 39/00 H01L 39/22-39/24 G11C 11/44 H03K 19/195

Claims (6)

(57) [Claims] 1. A superconducting memory cell array loop comprising a driving voltage generating unit including a driver gate circuit and a reset gate circuit and a superconducting memory cell array unit. A reset circuit in a superconducting memory circuit, comprising a gate circuit having an asymmetric threshold characteristic, and a DC current line magnetically coupled to the gate circuit. 2. A superconducting memory cell array loop comprising a driving voltage generating section including a driver gate circuit and a superconducting memory cell array section, wherein said driver gate circuit has a threshold voltage asymmetric with respect to a positive direction and a negative direction of an input current. A reset circuit in a superconducting storage circuit, characterized in that a gate circuit having characteristics is used, and a direct current line is magnetically coupled to the gate circuit. 3. A superconducting memory cell array loop comprising a driving voltage generating section including a driver gate circuit and a reset gate circuit and a superconducting memory cell array section, wherein a single Josephson junction and a superconducting wiring are used as the reset gate circuit. A magnetic coupling gate circuit magnetically coupled to a superconducting loop comprising a DC current line and a part of a bias line of the driver gate circuit are magnetically coupled to the superconducting loop. Reset circuit in conduction storage circuit. 4. A superconducting memory cell array loop comprising a driving voltage generating section including a driver gate circuit and a superconducting memory cell array section, wherein the driver gate circuit comprises a single Josephson junction and a superconducting wiring. Using a magnetic coupling gate circuit magnetically coupled to the loop,
A reset circuit in a superconducting storage circuit, wherein a direct current line and a part of a bias line of the driver gate circuit are magnetically coupled to the superconducting loop. 5. A superconducting memory cell array loop comprising a driving voltage generating section including a driver gate circuit and a reset gate circuit and a superconducting memory cell array section, wherein a DC current line as the reset gate circuit and a bias of the driver gate circuit are provided. A reset circuit in a superconducting memory circuit, wherein a coupling gate circuit in which a part of a line is magnetically coupled is used. 6. A superconducting memory cell array loop comprising a driving voltage generating section including a driver gate circuit and a superconducting memory cell array section, wherein the driver gate circuit includes a DC current line and a part of a bias line of the driver gate circuit. A reset circuit in a superconducting storage circuit, characterized in that a coupling gate circuit is used which is magnetically coupled to the circuit.