JPH02252195A - Josephson latch circuit - Google Patents

Abstract

PURPOSE:To use a Josephson latch circuit at the time of a unipolar AC driving system by providing a true signal input line and an auxiliary signal input line, directly connecting one line to a data holding loop and magnetically coupling the other line to one part of the data holding loop. CONSTITUTION:A result computed in an operational area is passed through a true signal line 17 or an auxiliary signal line 18 and inputted to a product arithmetic circuit 16 or 15. A latch enable signal is inputted to the circuits 15 and 16 and goes into a data write area and data are inputted through a true signal input line 1 or an auxiliary signal input line 2 to the data holding loop. When the computed result is 1, a true signal inputted and a Josephson joint 3 is switched. On the other hand, when the computed result is 0, an auxilia ry signal is inputted. Next, at the time of reading, a gate current is impressed to an interferometer gate circuit 7. When a permanent current flow in the data holding loop, the circuit 7 is switched and a signal appears in a true signal output line 12. When the permanent current does not flow in the above mentioned loop, an output signal appears in an auxiliary signal output line 13.

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a latch circuit using a Josephson junction, more specifically, a dual rail circuit that inputs and outputs a true signal and a complementary signal in the circuit. This invention relates to a latch circuit that temporarily stores information in a logic circuit of the system.

(Prior Art) Once switched to a voltage state, a Josephson junction element performs a latching operation in which the voltage state is maintained unless the power supply current is turned off. For this reason, in logic circuits using Josephson junctions, an AC power supply system in which the power supply current is reset to 0 once is common. In this power supply system, a latch circuit that holds the calculated results while the power supply current is 0 is essential. On the other hand, it is more difficult to construct an inverter in logic circuits using Josephson junctions than in semiconductors, and a dual rail system is generally adopted. The dual rail method is a circuit method in which the complementary signal of the input signal to the logic circuit is input at the same time, and the complementary signal of the output signal is also generated simultaneously in the logic circuit, and it uses an inverter that requires a timing signal. Since this is not necessary, the speed of the circuit can be increased. Therefore, a dual-rail type latch circuit is required in which both the true signal and the complementary signal are outputted from the above-mentioned latch circuit.

In the past, several latch circuits have been proposed and studied, and here, a conventional example shown in FIG. 4, which is superior in terms of the area occupied by the circuit, will be described as an example. The operation of this conventional latch circuit is described in the literature Journal of Applied Physics.
Physics) vol, 59(9), pp319
6-3201, so I will only briefly describe it here. FIG. 4 shows an equivalent circuit of a conventional example, in which 40 is a data input line, 41 is a latch enable signal line, 42, 43, 44, 47, 48 are Josephson junctions, 45 is an inductance, and 46 is a sense Signal input line, 4
9, 400, 401 are resistors, 402 is an auxiliary signal output line,
403 is a true signal output line, and Josephson junction 42
and an inductance 45 constitute a data holding loop. When writing data "1", a data signal and a latch enable signal are input to the data holding loop through the data input line and the latch enable signal line. This causes Josephson junction 42 to switch and store data in the data retention loop as a persistent current. The latch enable signal is used to notify the timing of writing to the latch circuit and to reset the data in the data holding loop. Since the latch circuit is used in bipolar AC driving, a latch enable signal having a polarity different from the human input signal input to the data holding loop during the previous machine cycle is input to the next stage. Therefore, the persistent current flowing in the data retention loop and the latch enable signal are superimposed at the Josephson junction 42.
2 switches and the persistent current is reset. Reading is performed when the sense gate current flowing through the sense signal input line 46 rises. When a persistent current flows in the data retention loop, the Josephson junctions 43 and 44 switch as the sense gate current rises, and an output appears on the true signal output line 403. If no persistent current flows in the data retention loop, the critical current value of the Josephson junction 47 is exceeded at the final stage when the sense gate current rises, and the Josephson junction 47 switches, followed by the Josephson junction 48. An output appears on the auxiliary signal output line 402. In the manner described above, a Josephson latch circuit can be realized.

(Problems to be Solved by the Invention) However, the above-described latch circuit has the following problems. In other words, when resetting data, a gate current with a polarity different from that of the previous machine cycle is always required. In other words, it can only be used in bipolar AC driven systems. Needless to say, Josephson integrated circuits require not only logic circuits but also memory circuits. Since most Josephson memory circuits carry information on the polarity of current or operate by superimposing currents, it is difficult to operate them with bipolar AC drive. Therefore, other driving methods include DC drive or unipolar AC drive, but considering that the logic circuit must also be driven, it is considered difficult to operate with DC drive. Therefore, a unipolar AC drive system was thought to be optimal, but in that case, as described above, a conventional latch circuit cannot be used.

(Means for Solving the Problems) According to the present invention, the data retention loop includes a single or multiple Josephson junctions and a superconducting inductance, and has a true signal input line and an auxiliary signal input line, of which one connected directly to the data retention loop and the other magnetically coupled to a portion of the data retention loop, the other having a sense circuit magnetically coupled to the portion of the data retention loop;
Furthermore, it has an output circuit that reads the information held in the data holding loop by the sense circuit and generates a true signal and a complementary signal, and one of the two input lines mentioned above is connected to a product of the true signal and the latch enable signal. A Josephson latch circuit is obtained, in which a signal obtained by multiplying a complementary signal and a latch enable signal is inputted, and a signal obtained by multiplying a complementary signal and a latch enable signal is inputted to the other side.

(Operation) In the data retention loop of the present invention, data is written by a switch of the Josephson junction, which is composed of a Josephson junction and an inductance.

When the data is "1", a true signal is input so as to exceed the critical current value of the Josephson junction, and a persistent current is written. In addition, when the data is 0'', the complementary signal is superimposed on the persistent current and input so as to exceed the critical current value of the Josephson junction, and the persistent current is reset. Each human input signal is multiplied by the latch enable signal. Since it is input later, there is no problem with the timing of manually inputting the human input signal.The data held in the data retention loop is read out by a sense gate circuit that is magnetically coupled to the data retention loop. , the true signal and complementary signal are output.

(Example) Figures 1 to 3 are diagrams for explaining the present invention in detail.
FIG. 1 shows an equivalent circuit of the embodiment, in which 1 is a true signal input line, 2 is a complementary signal input line, 3.8.19 is a Josephson junction, 4 and 5.6 are inductances, and 7 is an interferro signal input line. Meta-gate circuit, 9 is gate current line, 1
0.11 is an output resistance, 12 is a true signal output line, 13 is an auxiliary signal output line, 14 is a latch enable signal line, 15.
16 is a product calculation circuit, 17 is a true signal line, and 18 is a complementary signal line. Assuming that the phase difference of the order parameters of the Josephson junction 3 is θ, the current-phase characteristics of the current input from the true signal human power line 1 are as shown in FIG. In FIG. 2, 21 to 26 indicate operating points, respectively. This current-phase characteristic is determined by the critical current value of the Josephson junction 3 and the inductance values of the inductances 4 and 5.6, and can be set to have the characteristics as shown in the figure. Further, FIG. 3 is an example of the waveform of the gate current of a Josephson logic circuit, which schematically shows the case of unipolar AC drive, where 31 is an operating area, 32 is a data writing area, 33 is a data holding area, 34 indicates a machine cycle, and 35 indicates a data read area.

The results calculated in the operating region 31 shown in FIG.
Alternatively, it is input to 15. A latch enable signal is input to the product calculation circuits 15 and 16 and enters the data write area 32, and data is input to the data holding loop via the true signal input line 1 or the auxiliary signal input line 2. If the calculation result is 11111, the true signal is input and the Josephson junction 3 switches.

That is, in FIG. 2, the operating point passes through 21 and moves to 22. After the gate current falls, the operating point moves to 23, and data is held in the data holding area 330. on the other hand,
If the calculation result is 0'', the complementary signal is input manually.The current induced in the data retention loop by the complementary signal is in the opposite direction to the true signal in the Josephson junction 3, so the operating point changes from 23 to u, 25 and moves to 26 to reset the persistent current of the data retention loop.Next, at the time of reading, the current is passed through the gate current line between the data readout areas 35,
A gate current is applied to the interferometer game 1 circuit 7.

When a persistent current is flowing in the data holding loop, this interferometer gate circuit 7 is switched, data is read out, and a signal appears on the true signal output line. At this time, the gate current is also shunted to the resistor 10, but the resistors 10 and 11 can be appropriately selected so that this shunted current does not switch the Josephson junction 19. When no persistent current flows in the data retention loop, the Josephson junction 8 switches at the final stage of the rise of the gate current, and then the Josephson junction 19 switches and an output signal appears on the auxiliary signal output line. At this time, in the operating region, the gate current is
Even if the state of the data retention loop changes, the output will not be affected.

As described above, a Josephson latch circuit can be realized using this circuit. This circuit is a latch circuit using a dual rail system, and is a launch circuit used when using a unipolar AC drive system. A true signal and a complementary signal are generated as outputs.

(Effects of the Invention) The latch circuit of the present invention can be used in a unipolar AC drive system and does not require any timing sequence for its operation. Furthermore, a single Josephson junction is used for writing data, so the area occupied by the circuit can be reduced.

[Brief explanation of drawings]

1, 2, and 3 are diagrams for explaining the present invention in detail. FIG. 1 is an equivalent circuit diagram of an embodiment, FIG. 2 is a current-phase characteristic diagram of a data retention loop, and FIG. Figure 3 is a gate current waveform diagram of the unipolar AC drive system. FIG. 4 is an equivalent circuit diagram of a conventional example. The numbers in the diagram are 1... true signal input line, 2. ...Auxiliary signal input line, 3
．． 8.19...Josephson junction, 4,5.6...
Inductance, 7... Interferometer gate circuit, 9... Gate current line, 10.11... Output resistance, 12... True signal output line, 13... Auxiliary signal output line, 14... ...Latch enable signal line, 15.1
6... Product calculation circuit, 17... True signal line, 18...
Auxiliary signal lines, 21, 22, 23, 24, 25, 26...
Operating point, 31... Operating area, 32... Data writing area, 33... Data holding area, 34... Machine cycle, 35... Data reading area, 40...
Data input line, 41...Latch enable signal line, 4
2.43,44,47,48...Josephson junction,
45... Inductance, 46... Sense signal input line, 49, 400, 401... Resistor, 402... Complementary signal output line, 403... True signal output line.

Claims (1)

[Claims] It has a data retention loop consisting of a single or multiple Josephson junctions and a superconducting inductance, and has a true signal input line and an auxiliary signal input line, one of which is directly connected to the data retention loop, and the other of which is connected directly to the data retention loop. A sense circuit is magnetically coupled to a portion of the data retention loop, and a sense circuit is magnetically coupled to a portion of the data retention loop, and the sense circuit reads information retained in the data retention loop and determines a true signal. It has an output circuit that generates a complementary signal, and one of the two input lines mentioned above receives a signal obtained by multiplying the true signal and the latch enable signal, and the other receives a signal obtained by multiplying the complementary signal and the latch enable signal. A Josephson latch circuit characterized by the fact that a signal is input.